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AgeCommit message (Expand)Author
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-09-25Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2015-09-25arm: clarify the use of muldiv64()Laurent Vivier
2015-09-25arm: Remove ELF_MACHINE from cpu.hPeter Crosthwaite
2015-09-24hw/intc: Initial implementation of vGICv3Pavel Fedin
2015-09-24arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()Pavel Fedin
2015-09-15target-arm: Use new revbit functionsRichard Henderson
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias
2015-09-14target-arm: Use tcg_gen_extrh_i64_i32Richard Henderson
2015-09-14target-arm: Recognize RORRichard Henderson
2015-09-14target-arm: Eliminate unnecessary zero-extend in disas_bitfieldRichard Henderson
2015-09-14target-arm: Recognize UXTB, UXTH, LSR, LSLRichard Henderson
2015-09-14target-arm: Recognize SXTB, SXTH, SXTW, ASRRichard Henderson
2015-09-14target-arm: Implement fcsel with movcondRichard Henderson
2015-09-14target-arm: Implement ccmp branchlessRichard Henderson
2015-09-14target-arm: Use setcond and movcond for cselRichard Henderson
2015-09-14target-arm: Handle always condition codes within arm_test_ccRichard Henderson
2015-09-14target-arm: Introduce DisasCompareRichard Henderson
2015-09-14target-arm: Share all common TCG temporariesRichard Henderson
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
2015-09-11typofixes - v4Veres Lajos
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias
2015-09-08target-arm: Log the target EL when taking exceptionsEdgar E. Iglesias
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin
2015-09-07target-arm: Refactor CPU affinity handlingPavel Fedin
2015-09-07target-arm: Fix arm_excp_unmasked() functionSergey Sorokin
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite
2015-09-07arm: cpu: assert() on no-EL2 virt IRQ error condition.Peter Crosthwaite
2015-09-07target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell
2015-09-07target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter blockPeter Maydell
2015-09-07target-arm/arm-semi.c: Implement A64 specific SyncCacheRange callPeter Maydell
2015-09-07target-arm/arm-semi.c: Support widening APIs to 64 bitsPeter Maydell
2015-09-07target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'Peter Maydell
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington
2015-09-07target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdbPeter Maydell
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