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2015-06-15target-arm: Correct "preferred return address" for cpreg access exceptionsPeter Maydell
The architecture defines that when taking an exception trying to access a coprocessor register, the "preferred return address" for the exception is the address of the instruction that caused the exception. Correct an off-by-4 error which meant we were returning the address after the instruction for traps which happened because of a failure of a runtime access-check function on an AArch32 register. (Traps caused by translate-time checkable permissions failures had the correct address, as did traps on AArch64 registers.) This fixes https://bugs.launchpad.net/qemu/+bug/1463338 Reported-by: Robert Buhren <robert@robertbuhren.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1433861440-30133-1-git-send-email-peter.maydell@linaro.org
2015-06-15arm: helper: rename get_phys_addr_mpuPeter Crosthwaite
This get_phys_addr is really for pmsav5. Rename it accordingly. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: bf4b019aa87d682a45998105ef8e4d4e97a5e117.1434066412.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Add has-mpu propertyPeter Crosthwaite
For processors that support MPUs, add a property to de-feature it. This is similar to the implementation of the EL3 feature. The processor definition in init sets ARM_FEATURE_MPU if it can support an MPU. post_init exposes the property, defaulting to true. If cleared by the instantiator, ARM_FEATURE_MPU is then removed at realize time. This is to support R profile processors that may or may-not have an MPU configured. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 632918cc48786e868ea18aa6bd12f70597994cad.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Implement uniprocessor with MP configPeter Crosthwaite
Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Refactor get_phys_addr FSR return mechanismPeter Crosthwaite
Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a209e3d8ae00cda55260c970891f520210e26bad.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: helper: Factor out CP regs common to [pv]msaPeter Crosthwaite
V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 284db78a43c63c9bfbb60de539672c361bcb6af8.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Don't add v7mp registers in MPU systemsPeter Crosthwaite
These registers are VMSA specific so they should be conditional on VMSA (i.e. !MPU). Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7bb8843e45f2635c6b7a583c5bb5da51ed4442a0.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15arm: Do not define TLBTR in PMSA systemsPeter Crosthwaite
If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b03fea3840207edf633f5c9189400c3dd6a28d14.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Add the THUMB_DSP featureAurelio C. Remonda
Create an ARM_FEATURE_THUMB_DSP controlling the Thumb encodings of the 85 DSP instructions (these are all Thumb2). This is enabled for all non-M-profile CPUs with Thumb2 support, as the instructions are mandatory for R and A profiles. On M profile they are optional and not present in the Cortex-M3 (though they are in the M4). The effect of this commit is that we will now treat the DSP encodings as illegal instructions on M3, when previously we incorrectly implemented them. Signed-off-by: Aurelio C. Remonda <aurelioremonda@gmail.com> Message-id: 1434311355-26554-1-git-send-email-aurelioremonda@gmail.com [PMM: added clz/crc32/crc32c and default case to the early-decode switch; minor format/spacing fixups; reworded commit message a bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin
When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: add AArch32 MIDR aliases in ARMv8Sergey Fedorov
According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-3-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Fix REVIDR reset valueSergey Fedorov
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-2-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm/kvm64: Add cortex-a53 cpu supportShannon Zhao
Since commit e353102(target-arm: cpu64: Add support for Cortex-A53) has added Cortex-A53 cpu support for target-arm, this patch just enables it for kvm-arm. Here adding XGENE_POTENZA just makes the enum continuous. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1433207452-4512-2-git-send-email-shannon.zhao@linaro.org [PMM: Don't add the CPU types to cpus_to_try[]; this array only lists old CPUs which were supported in pre-PREFERRED_TARGET kernels] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm/cpu.h: remove pending_exceptionAlex Bennée
This isn't used by any of the code. In fact it looks like it was never used as it came in with ARMv7 support. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1434020015-8868-1-git-send-email-alex.bennee@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: use extended address bits from supersection short descriptorSergey Fedorov
Since ARMv7 with LPAE support, a supersection short translation table descriptor has had extended base address fields which hold bits 39:32 of translated address. These fields are IMPDEF in ARMv6 and ARMv7 without LPAE support. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433235718-30485-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Handle "extended small page" descriptors correctlyPeter Maydell
The old ARMv5-style page table format includes a kind of second level descriptor named the "extended small page" format, whose primary purpose is to allow specification of the TEX memory attribute bits on a 4K page. This exists on ARMv6 and also (as an implementation extension) on XScale CPUs; it's UNPREDICTABLE on v5. We were mishandling this in two ways: (1) we weren't implementing it for v6 (probably never noticed because Linux will use the new-style v6 page table format there) (2) we were not correctly setting the page_size, which is 4K, not 1K The latter bug went unnoticed for years because the only thing which the page_size affects is which TLB entries get flushed when the guest does a TLB invalidate on an address in the page, and prior to commit 2f0d8631b7 we were doing a full TLB flush very frequently due to Linux's habit of writing the SCTLR pointlessly a lot. (We can assume that after commit 2f0d8631b7 the bug went unnoticed for a year because nobody's actually using the Zaurus/XScale emulation...) Report the correct page size for these descriptors, and permit them on ARMv6 CPUs. This fixes a problem where a kernel image for Zaurus can boot the kernel OK but gets random segfaults when it tries to run userspace programs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1432844085-16441-1-git-send-email-peter.maydell@linaro.org
2015-06-12migration: Use normal VMStateDescriptions for SubsectionsJuan Quintela
We create optional sections with this patch. But we already have optional subsections. Instead of having two mechanism that do the same, we can just generalize it. For subsections we just change: - Add a needed function to VMStateDescription - Remove VMStateSubsection (after removal of the needed function it is just a VMStateDescription) - Adjust the whole tree, moving the needed function to the corresponding VMStateDescription Signed-off-by: Juan Quintela <quintela@redhat.com>
2015-06-02target-arm: Remove v8_ prefix from names of non-v8-specific cpreg arraysPeter Maydell
The ARMCPRegInfo arrays v8_el3_no_el2_cp_reginfo and v8_el2_cp_reginfo are actually used on non-v8 CPUs as well. Remove the incorrect v8_ prefix from their names. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1433182716-6400-1-git-send-email-peter.maydell@linaro.org
2015-06-02kvm: introduce kvm_arch_msi_data_to_gsiEric Auger
On ARM the MSI data corresponds to the shared peripheral interrupt (SPI) ID. This latter equals to the SPI index + 32. to retrieve the SPI index, matching the gsi, an architecture specific function is introduced. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02Revert "target-arm: Avoid g_hash_table_get_keys()"Markus Armbruster
Since we now require GLib 2.22+ (commit f40685c), we don't have to work around lack of g_hash_table_get_keys() anymore. This reverts commit 82a3a11897308b606120f7235001e87809708f85. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-id: 1432749090-4698-1-git-send-email-armbru@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TLBI_VAE2{IS}Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-11-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TLBI_ALLE2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-10-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TLBI_ALLE1{IS}Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-9-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TTBR0_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-8-git-send-email-edgar.iglesias@gmail.com [PMM: Switch to preferred opc1/crm order for 64-bit AArch32 cpregs; drop unneeded use of vmsa_ttbr_writefn] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TPIDR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-7-git-send-email-edgar.iglesias@gmail.com [PMM: reordered fields into preferred opc0/opc1/crn/crm/opc2 order] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add SCTLR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-6-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add TCR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add MAIR_EL2Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Break down TLB_LOCKDOWNEdgar E. Iglesias
Break down the overly broad wildcard definition of TLB_LOCKDOWN down to v7 level. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-3-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Correct check for non-EL3Edgar E. Iglesias
This fixes a compile warning from clang 3.5 (the assertion could never fire). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: John Snow <jsnow@redhat.com> [PMM: added note in commit message that this is fixing a build warning] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strdPeter Maydell
A LDRD or STRD where rd is not an even number is UNPREDICTABLE. We were letting this fall through, which is OK unless rd is 15, in which case we would attempt to do a load_reg or store_reg to a nonexistent r16 for the second half of the double-word. Catch the odd-numbered-rd cases and UNDEF them instead. To do this we rearrange the structure of the code a little so we can put the UNDEF catches at the top before we've allocated TCG temporaries. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1431348973-21315-1-git-send-email-peter.maydell@linaro.org
2015-05-29target-arm: Add WFx instruction trap supportGreg Bellows
Add support for trapping WFI and WFE instructions to the proper EL when SCTLR/SCR/HCR settings apply. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: removed unnecessary tweaking of syn_wfx() prototype; use raise_exception(); don't trap on WFE (and add comment explaining why not); remove unnecessary ARM_FEATURE checks; trap to EL3, not EL1, if in S-EL0 and SCTLR check fires] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Don't halt on WFI unless we don't have any workPeter Maydell
Just NOP the WFI instruction if we have work to do. This doesn't make much difference currently (though it does avoid jumping out to the top level loop and immediately restarting), but the distinction between "halt" and "don't halt" will become more important when the decision to halt requires us to trap to a higher exception level instead. Suggested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Move TB flags down to fill gapPeter Maydell
Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows
Extend the ARM disassemble context to take a target exception EL instead of a boolean enable. This change reverses the polarity of the check making a value of 0 indicate floating point enabled (no exception). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: Use a common TB flag field for AArch32 and AArch64; CPTR_EL2 exists in v7; CPTR_EL2 should trap for EL2 accesses; CPTR_EL2 should not trap for secure accesses; CPTR_EL3 should trap for EL3 accesses; CPACR traps for secure accesses should trap to EL3 if EL3 is AArch32] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell
Currently we keep the TB flags PSTATE_SS and SS_ACTIVE in different bit positions for AArch64 and AArch32. Replace these separate definitions with a single common flag in the upper part of the flags word. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Add AArch64 CPTR registersGreg Bellows
Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Allow cp access functions to indicate traps to EL2 or EL3Peter Maydell
Some coprocessor access functions will need to indicate that the instruction should trap to EL2 or EL3 rather than the default target exception level; add corresponding CPAccessResult enum entries and handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows
Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Make raise_exception() take syndrome and target ELPeter Maydell
Rather than making every caller of raise_exception set the syndrome and target EL by hand, make these arguments to raise_exception() and have that do the job. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Set exception target EL in tlb_fillPeter Maydell
Set the exception target EL for MMU faults in tlb_fill. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell
Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Set correct syndrome for faults on MSR DAIF*, immPeter Maydell
If the SCTLR.UMA trap bit is set then attempts by EL0 to update the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" instructions will raise an exception. We were failing to set the syndrome information for this exception, which meant that it would be reported as a repeat of whatever the previous exception was. Set the correct syndrome information. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Extend helpers to route exceptionsGreg Bellows
Updated the various helper routines to set the target EL as needed using a dedicated function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-3-git-send-email-greg.bellows@linaro.org [PMM: Also set target_el in fault cases in access_check_cp_reg()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows
Add a CPU state exception target EL field that will be used for communicating the EL to which an exception should be routed. Add a disassembly context field for tracking the EL3 architecture needed for determining the target exception EL. Add a target EL argument to the generic exception helper for callers to specify the EL to which the exception should be routed. Extended the helper to set the newly added CPU state exception target el. Added a function for setting the target exception EL and updated calls to helpers to call it. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Remove unneeded '+'Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1431499963-1019-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Correct accessfn for CNTV_TVAL_EL0Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1431499963-1019-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Correct accessfn for CNTP_{CT}VAL_EL0Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1431499963-1019-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Add WFx syndrome functionGreg Bellows
Adds a utility function for creating a WFx exception syndrome Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-9-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18target-arm: Add EL3 and EL2 TCR checkingGreg Bellows
Updated get_phys_addr_lpae to check the appropriate TTBCR/TCR depending on the current EL. Support includes using the different TCR format as well as checks to insure TTBR1 is not used when in EL2 or EL3. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-8-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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