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2012-03-15target-arm: Decode SETEND correctly in ThumbPeter Maydell
Decode the SETEND instruction correctly in Thumb mode, rather than accidentally treating it like CPS. We don't support BE8 mode, but this change brings the Thumb mode in to line with behaviour in ARM mode: 'SETEND BE' is not supported and will provoke an UNDEF exception, but 'SETEND LE' is correctly handled as a no-op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Daniel Forsgren <daniel.forsgren@enea.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2012-03-15target-arm: Clear IT bits when taking exceptions in v7MPeter Maydell
When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-15target-arm: Fix typo in ARM946 cp15 c5 handlingPeter Maydell
Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling (instruction access permission bits) that meant it would return the data access permission bits by mistake. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber
Scripted conversion: for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done All occurrences of CPUArchState are expected to be replaced by QOM CPUState, once all targets are QOM'ified and common fields have been extracted. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14target-arm: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-28target-arm: Clean includesStefan Weil
Remove some include statements which are not needed. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-17target-arm/helper.c: tb_flush() on CPU resetPeter Maydell
Since target-arm has some CPUState fields for which we take the approach of baking assumptions about them into translated code and then calling tb_flush() when the fields change, we must also tb_flush on CPU reset, because reset is a change of those fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-02-17target-arm/helper.c: Correct FPSID value for Cortex-A9Peter Maydell
The correct FPSID for the Cortex-A9 (according to the TRM) is 0x41033090 for the r0p0 that we claim to model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-01-25Add Cortex-A15 CPU definitionPeter Maydell
Add a definition of a Cortex-A15 CPU. Note that for the moment we do not implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc) This CPU model is sufficient to boot a Linux kernel which has been compiled for an A15 without LPAE enabled. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25Add dummy implementation of generic timer cp15 registersPeter Maydell
Add a dummy implementation of the cp15 registers for the generic timer (found in the Cortex-A15), just sufficient for Linux to decide that it can't use it. This requires at least CNTP_CTL and CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25arm: store the config_base_register during cpu_resetMark Langsdorf
Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25target-arm/helper.c: Don't assume softfloat int32 is 32 bits onlyPeter Maydell
In the helper routines for VCVT float-to-int conversions, add an explicit cast rather than relying on the softfloat int32 type being exactly 32 bits wide (which it is not guaranteed to be). Without this, if the softfloat type was 64 bits wide we would get zero-extension of the 32 bit value from the ARM register rather than sign-extension, since TCG i32 values are passed as uint32_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25target-arm: Fix implementation of TLB invalidate operationsPeter Maydell
Fix some bugs in the implementation of the TLB invalidate operations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since tlb_flush() currently ignores that argument, but is semantically incorrect * 'invalidate by address for all ASIDs' was implemented as flushing the whole TLB, which invalidates much more than strictly necessary. Use tlb_flush_page() instead. We also annotate the ops with the ARM ARM official acronyms. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13arm: Add dummy support for co-processor 15's secure config registerRob Herring
Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13target-arm: Fix errors in decode of M profile CPSPeter Maydell
Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17 This fixes an issue reported as LP:913925. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05arm: add dummy A9-specific cp15 registersMark Langsdorf
Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05target-arm: Ignore attempts to set invalid modes in CPSRPeter Maydell
Ignore attempts to set the CPSR mode field to an invalid value. This is UNPREDICTABLE, but we should not cpu_abort() for things a malicious guest (or a confused user on the gdbstub interface) can provoke. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05target-arm: Don't use cpu_single_env in bank_number()Peter Maydell
Avoid using cpu_single_env in bank_number() -- if we were called via the gdb stub reading or writing the CPSR then it is NULL and we will segfault if we take the cpu_abort(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer VFPv3 feature from VFPv4Andreas Färber
VFP4 => VFP3 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer VFP feature from VFPv3Andreas Färber
VFP3 => VFP Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer Thumb division feature from M profileAndreas Färber
M => THUMB_DIV Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer Thumb2 feature from ARMv7Andreas Färber
V7 => THUMB2 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer AUXCR feature from ARMv6Andreas Färber
V6 && !M => AUXCR Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv6(K) feature from ARMv7Andreas Färber
V7 && M => V6 V7 && !M => V6K Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv6 feature from v6KAndreas Färber
V6K => V6 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv5 feature from ARMv6Andreas Färber
V6 => V5 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv4T feature from ARMv5Andreas Färber
V5 => V4T Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13arm: Fix CP15 FSR (C5) domain settingJean-Christophe DUBOIS
Return the correct value in the domain field in the cp15 DFSR (C5) -- bug noticed during Xvisor development. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> [Peter Maydell: reworded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-05target-arm/helper.c: Don't allocate TCG resources unless TCG enabledPeter Maydell
Don't call arm_translate_init() (which allocates TCG resources) unless TCG is enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-12-05target-arm/translate.c: Fix slightly misleading comment in Thumb decoderPeter Maydell
Clarify some slightly misleading comments in the Thumb decoder's handling of the memory hint space -- in particular one code path marked as 'UNPREDICTABLE or unallocated hint' also includes some legitimate preload instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-10-20target-arm: Fix use of free() in cpu_arm_close()Andreas Färber
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm/machine.c: Restore VFP registers correctlyDmitry Koshelev
Fix the restoring of VFP registers on vmload. Signed-off-by: Dmitry Koshelev <karaghiozis@gmail.com> Reviewed-by: Juan Quintela <quintela@redhat.com> [peter.maydell: improved commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell
Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Add ARM UDIV/SDIV supportPeter Maydell
Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: v6 media multiply space: UNDEF on unassigned encodingsPeter Maydell
Clean up the decoding of the v6 media multiply space so that we UNDEF on unassigned encodings rather than randomly interpreting them as some instruction in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19rsqrte_f32: No need to copy sign bit.Christophe LYON
Indeed, the result is known to be always positive. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-10Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori
2011-10-08ARM: fix segfaultBlue Swirl
Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33, target-arm/op_helper.c missed a change unlike all other targets. This lead to a NULL pointer dereferences. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-05target-arm: Fix typoAndreas Färber
The command line option is called -kernel, not -kenrel. Cc: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-20Use glib memory allocation and free functionsAnthony Liguori
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-08-09Merge remote-tracking branch 'pm-arm/for-upstream' into pmEdgar E. Iglesias
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30exec.h cleanupBlue Swirl
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-26target-arm: Don't print debug messages for various UNDEF casesPeter Maydell
Remove some stray printfs for cases which don't generally happen (some VFP UNDEF cases, reads and writes to unknown cp14 registers); we should simply generate an UNDEF when the instruction is executed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assertPeter Maydell
VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF. This avoids a TCG assert later when the VCVTT/VCVTB code tries to use a source register that wasn't ever set up. We pull the check for the presence of the half-precision extension up in to this common code as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTMPeter Maydell
Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. In particular, we now generate an undef exception for overlarge imm8 values rather than generating 1000+ TCG ops and hitting an assertion. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-07-26target-arm: Support v6 barriers in linux-user modePeter Maydell
ARMv6 implemented various operations as special cases of cp15 accesses which are true instructions in v7; this includes barriers (DMB, DSB, ISB). Catch this special case at translate time, so that it works in linux-user mode (which doesn't provide a functional get_cp15 helper) as well as system mode. Includes minor cleanup of the existing cases (single switch statement, and doing the "OK in user mode?" test explicitly rather than hiding it in cp15_user_ok()). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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