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AgeCommit message (Expand)Author
2014-02-26target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell
2014-02-26target-arm: Implement AArch64 MIDR_EL1Peter Maydell
2014-02-26target-arm: Implement AArch64 CurrentEL sysregPeter Maydell
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell
2014-02-26target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell
2014-02-26arm: vgic device control api supportChristoffer Dall
2014-02-26target-arm: Load correct access bits from ARMv5 level 2 page table descriptorsPeter Maydell
2014-02-26target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS opsPeter Maydell
2014-02-20target-arm: A64: Implement unprivileged load/storePeter Maydell
2014-02-20target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell
2014-02-20target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell
2014-02-20target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell
2014-02-20target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell
2014-02-20target-arm: A64: Implement store-exclusive for system modePeter Maydell
2014-02-20target-arm: Fix incorrect type for value argument to write_raw_cp_regPeter Maydell
2014-02-20target-arm: Remove failure status return from read/write_raw_cp_regPeter Maydell
2014-02-20target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell
2014-02-20target-arm: Drop success/fail return from cpreg read and write functionsPeter Maydell
2014-02-20target-arm: Convert miscellaneous reginfo structs to accessfnPeter Maydell
2014-02-20target-arm: Convert generic timer reginfo to accessfnPeter Maydell
2014-02-20target-arm: Convert performance monitor reginfo to accessfnPeter Maydell
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell
2014-02-20target-arm: Stop underdecoding ARM946 PRBS registersPeter Maydell
2014-02-20target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell
2014-02-20target-arm: Remove unused ARMCPUState sr substructPeter Maydell
2014-02-20target-arm: Restrict check_ap() use of S and R bits to v6 and earlierPeter Maydell
2014-02-20target-arm: Define names for SCTLR bitsPeter Maydell
2014-02-20target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUsPeter Maydell
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell
2014-02-20target-arm: A64: Implement floating point pairwise insnsAlex Bennée
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée
2014-02-20target-arm: A64: Implement scalar three different instructionsPeter Maydell
2014-02-20target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell
2014-02-20target-arm: A64: Implement long vector x indexed insnsPeter Maydell
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias
2014-02-08disas: Implement disassembly output for A64Claudio Fontana
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell
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