Age | Commit message (Expand) | Author |
2014-03-13 | cputlb: Change tlb_set_page() argument to CPUState | Andreas Färber |
2014-03-13 | cputlb: Change tlb_flush() argument to CPUState | Andreas Färber |
2014-03-13 | cputlb: Change tlb_flush_page() argument to CPUState | Andreas Färber |
2014-03-13 | exec: Change cpu_abort() argument to CPUState | Andreas Färber |
2014-03-13 | translate-all: Change cpu_restore_state() argument to CPUState | Andreas Färber |
2014-03-13 | cpu-exec: Change cpu_loop_exit() argument to CPUState | Andreas Färber |
2014-03-13 | exec: Change tlb_fill() argument to CPUState | Andreas Färber |
2014-03-13 | cpu: Move breakpoints field from CPU_COMMON to CPUState | Andreas Färber |
2014-03-13 | cpu: Move opaque field from CPU_COMMON to CPUState | Andreas Färber |
2014-03-13 | cpu: Move exception_index field from CPU_COMMON to CPUState | Andreas Färber |
2014-03-13 | cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook | Andreas Färber |
2014-03-13 | cpu: Factor out cpu_generic_init() | Andreas Färber |
2014-03-13 | cpu: Turn cpu_has_work() into a CPUClass hook | Andreas Färber |
2014-03-13 | target-arm: Clean up ENV_GET_CPU() usage | Andreas Färber |
2014-03-10 | target-arm: Implement WFE as a yield operation | Peter Maydell |
2014-03-10 | target-arm: Fix intptr_t vs tcg_target_long | Richard Henderson |
2014-03-10 | target-arm: Implements the ARM PMCCNTR register | Alistair Francis |
2014-03-10 | target-arm: Fix incorrect setting of E bit in CPSR | Peter Maydell |
2014-02-26 | target-arm: Add support for AArch32 ARMv8 CRC32 instructions | Will Newton |
2014-02-26 | target-arm: Add utility function for checking AA32/64 state of an EL | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 view of CPACR | Peter Maydell |
2014-02-26 | target-arm: A64: Implement MSR (immediate) instructions | Peter Maydell |
2014-02-26 | target-arm: Store AIF bits in env->pstate for AArch32 | Peter Maydell |
2014-02-26 | target-arm: A64: Implement WFI | Peter Maydell |
2014-02-26 | target-arm: Get MMU index information correct for A64 code | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 dummy breakpoint and watchpoint registers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 ID and feature registers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 generic timers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 MPIDR | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 TTBR* | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 VBAR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 TCR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 SCTLR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 memory attribute registers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 dummy MDSCR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 TLB invalidate ops | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 cache invalidate/clean ops | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 MIDR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 CurrentEL sysreg | Peter Maydell |
2014-02-26 | target-arm: A64: Make cache ID registers visible to AArch64 | Peter Maydell |
2014-02-26 | target-arm: Fix raw read and write functions on AArch64 registers | Peter Maydell |
2014-02-26 | arm: vgic device control api support | Christoffer Dall |
2014-02-26 | target-arm: Load correct access bits from ARMv5 level 2 page table descriptors | Peter Maydell |
2014-02-26 | target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops | Peter Maydell |
2014-02-20 | target-arm: A64: Implement unprivileged load/store | Peter Maydell |
2014-02-20 | target-arm: A64: Implement narrowing three-reg-diff operations | Peter Maydell |
2014-02-20 | target-arm: A64: Implement the wide 3-reg-different operations | Peter Maydell |
2014-02-20 | target-arm: A64: Add most remaining three-reg-diff widening ops | Peter Maydell |
2014-02-20 | target-arm: A64: Add opcode comments to disas_simd_three_reg_diff | Peter Maydell |