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AgeCommit message (Expand)Author
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber
2012-10-28target-arm: rename helper flagsAurelien Jarno
2012-10-24target-arm: Remove out of date FIXME regarding saturating arithmeticPeter Maydell
2012-10-24target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell
2012-10-24target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell
2012-10-24arm-semi.c: Handle get/put_user() failure accessing argumentsPeter Maydell
2012-10-23Rename target_phys_addr_t to hwaddrAvi Kivity
2012-10-19target-arm/neon_helper: Remove obsolete FIXME commentPeter Maydell
2012-10-17target-arm/translate: Fix RRX operandsPeter Crosthwaite
2012-10-05target-arm: Drop unused DECODE_CPREG_CRN macroPeter Maydell
2012-10-05target-arm: use deposit instead of hardcoded versionAurelien Jarno
2012-10-05target-arm: mark a few integer helpers const and pureAurelien Jarno
2012-10-05target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno
2012-10-05target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno
2012-10-05target-arm: use globals for CC flagsAurelien Jarno
2012-10-05target-arm: Reinstate display of VFP registers in cpu_dump_statePeter Maydell
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl
2012-09-15target-arm: convert remaining helpersBlue Swirl
2012-09-15target-arm: convert void helpersBlue Swirl
2012-09-10target-arm: Fix potential buffer overflowStefan Weil
2012-08-22arm-semi: don't leak 1KB user string lock buffer upon TARGET_SYS_OPENJim Meyering
2012-08-10target-arm: Fix typos in commentsPeter Maydell
2012-08-10arm: translate: comment typo - s/middel/middle/Peter A. G. Crosthwaite
2012-07-12target-arm: Add support for long format translation table walksPeter Maydell
2012-07-12target-arm: Implement TTBCR changes for LPAEPeter Maydell
2012-07-12target-arm: Implement long-descriptor PAR formatPeter Maydell
2012-07-12target-arm: Use target_phys_addr_t in get_phys_addr()Peter Maydell
2012-07-12target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAEPeter Maydell
2012-07-12target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAEPeter Maydell
2012-07-12target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registersPeter Maydell
2012-07-12target-arm: Extend feature flags to 64 bitsPeter Maydell
2012-07-12target-arm: Implement privileged-execute-never (PXN)Peter Maydell
2012-07-12ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bitsPeter Maydell
2012-07-12target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell
2012-07-12target-arm: Fix some copy-and-paste errors in cp register namesPeter Maydell
2012-07-12target-arm: Fix typo that meant TTBR1 accesses went to TTBR0Peter Maydell
2012-07-12target-arm: Fix CP15 based WFIPaul Brook
2012-06-20target-arm: Remove ARM_CPUID_* macrosPeter Maydell
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell
2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell
2012-06-20target-arm: Remove c0_cachetype CPUARMState fieldPeter Maydell
2012-06-20target-arm: Convert final ID registersPeter Maydell
2012-06-20target-arm: Convert MPIDRPeter Maydell
2012-06-20target-arm: Convert cp15 cache ID registersPeter Maydell
2012-06-20target-arm: Convert cp15 crn=0 crm={1,2} feature registersPeter Maydell
2012-06-20target-arm: Convert cp15 crn=1 registersPeter Maydell
2012-06-20target-arm: Convert cp15 crn=9 registersPeter Maydell
2012-06-20target-arm: Convert cp15 crn=6 registersPeter Maydell
2012-06-20target-arm: convert cp15 crn=7 registersPeter Maydell
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