Age | Commit message (Expand) | Author |
2012-09-27 | Emit debug_insn for CPU_LOG_TB_OP_OPT as well. | Richard Henderson |
2012-09-15 | target-arm: final conversion to AREG0 free mode | Blue Swirl |
2012-09-15 | target-arm: convert remaining helpers | Blue Swirl |
2012-09-15 | target-arm: convert void helpers | Blue Swirl |
2012-09-10 | target-arm: Fix potential buffer overflow | Stefan Weil |
2012-08-22 | arm-semi: don't leak 1KB user string lock buffer upon TARGET_SYS_OPEN | Jim Meyering |
2012-08-10 | target-arm: Fix typos in comments | Peter Maydell |
2012-08-10 | arm: translate: comment typo - s/middel/middle/ | Peter A. G. Crosthwaite |
2012-07-12 | target-arm: Add support for long format translation table walks | Peter Maydell |
2012-07-12 | target-arm: Implement TTBCR changes for LPAE | Peter Maydell |
2012-07-12 | target-arm: Implement long-descriptor PAR format | Peter Maydell |
2012-07-12 | target-arm: Use target_phys_addr_t in get_phys_addr() | Peter Maydell |
2012-07-12 | target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE | Peter Maydell |
2012-07-12 | target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE | Peter Maydell |
2012-07-12 | target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers | Peter Maydell |
2012-07-12 | target-arm: Extend feature flags to 64 bits | Peter Maydell |
2012-07-12 | target-arm: Implement privileged-execute-never (PXN) | Peter Maydell |
2012-07-12 | ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits | Peter Maydell |
2012-07-12 | target-arm: Fix TCG temp handling in 64 bit cp writes | Peter Maydell |
2012-07-12 | target-arm: Fix some copy-and-paste errors in cp register names | Peter Maydell |
2012-07-12 | target-arm: Fix typo that meant TTBR1 accesses went to TTBR0 | Peter Maydell |
2012-07-12 | target-arm: Fix CP15 based WFI | Paul Brook |
2012-06-20 | target-arm: Remove ARM_CPUID_* macros | Peter Maydell |
2012-06-20 | target-arm: Remove remaining old cp15 infrastructure | Peter Maydell |
2012-06-20 | target-arm: Move block cache ops to new cp15 framework | Peter Maydell |
2012-06-20 | target-arm: Remove c0_cachetype CPUARMState field | Peter Maydell |
2012-06-20 | target-arm: Convert final ID registers | Peter Maydell |
2012-06-20 | target-arm: Convert MPIDR | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 cache ID registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=0 crm={1,2} feature registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=1 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=9 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=6 registers | Peter Maydell |
2012-06-20 | target-arm: convert cp15 crn=7 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 VA-PA translation registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 MMU TLB control | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=15 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=10 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=13 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 crn=2 registers | Peter Maydell |
2012-06-20 | target-arm: Convert MMU fault status cp15 registers | Peter Maydell |
2012-06-20 | target-arm: Convert cp15 c3 register | Peter Maydell |
2012-06-20 | target-arm: Convert generic timer cp15 regs | Peter Maydell |
2012-06-20 | target-arm: Convert performance monitor registers | Peter Maydell |
2012-06-20 | target-arm: Convert TLS registers | Peter Maydell |
2012-06-20 | target-arm: Convert WFI/barriers special cases to cp_reginfo | Peter Maydell |
2012-06-20 | target-arm: Convert TEECR, TEEHBR to new scheme | Peter Maydell |
2012-06-20 | target-arm: Convert debug registers to cp_reginfo | Peter Maydell |
2012-06-20 | target-arm: Add register_cp_regs_for_features() | Peter Maydell |
2012-06-20 | target-arm: Remove old cpu_arm_set_cp_io infrastructure | Peter Maydell |