Age | Commit message (Expand) | Author |
2014-02-26 | target-arm: Add support for AArch32 ARMv8 CRC32 instructions | Will Newton |
2014-02-26 | target-arm: Add utility function for checking AA32/64 state of an EL | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 view of CPACR | Peter Maydell |
2014-02-26 | target-arm: A64: Implement MSR (immediate) instructions | Peter Maydell |
2014-02-26 | target-arm: Store AIF bits in env->pstate for AArch32 | Peter Maydell |
2014-02-26 | target-arm: A64: Implement WFI | Peter Maydell |
2014-02-26 | target-arm: Get MMU index information correct for A64 code | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 dummy breakpoint and watchpoint registers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 ID and feature registers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 generic timers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 MPIDR | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 TTBR* | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 VBAR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 TCR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 SCTLR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 memory attribute registers | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 dummy MDSCR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 TLB invalidate ops | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 cache invalidate/clean ops | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 MIDR_EL1 | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 CurrentEL sysreg | Peter Maydell |
2014-02-26 | target-arm: A64: Make cache ID registers visible to AArch64 | Peter Maydell |
2014-02-26 | target-arm: Fix raw read and write functions on AArch64 registers | Peter Maydell |
2014-02-26 | arm: vgic device control api support | Christoffer Dall |
2014-02-26 | target-arm: Load correct access bits from ARMv5 level 2 page table descriptors | Peter Maydell |
2014-02-26 | target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops | Peter Maydell |
2014-02-20 | target-arm: A64: Implement unprivileged load/store | Peter Maydell |
2014-02-20 | target-arm: A64: Implement narrowing three-reg-diff operations | Peter Maydell |
2014-02-20 | target-arm: A64: Implement the wide 3-reg-different operations | Peter Maydell |
2014-02-20 | target-arm: A64: Add most remaining three-reg-diff widening ops | Peter Maydell |
2014-02-20 | target-arm: A64: Add opcode comments to disas_simd_three_reg_diff | Peter Maydell |
2014-02-20 | target-arm: A64: Implement store-exclusive for system mode | Peter Maydell |
2014-02-20 | target-arm: Fix incorrect type for value argument to write_raw_cp_reg | Peter Maydell |
2014-02-20 | target-arm: Remove failure status return from read/write_raw_cp_reg | Peter Maydell |
2014-02-20 | target-arm: Remove unnecessary code now read/write fns can't fail | Peter Maydell |
2014-02-20 | target-arm: Drop success/fail return from cpreg read and write functions | Peter Maydell |
2014-02-20 | target-arm: Convert miscellaneous reginfo structs to accessfn | Peter Maydell |
2014-02-20 | target-arm: Convert generic timer reginfo to accessfn | Peter Maydell |
2014-02-20 | target-arm: Convert performance monitor reginfo to accessfn | Peter Maydell |
2014-02-20 | target-arm: Split cpreg access checks out from read/write functions | Peter Maydell |
2014-02-20 | target-arm: Stop underdecoding ARM946 PRBS registers | Peter Maydell |
2014-02-20 | target-arm: Log bad system register accesses with LOG_UNIMP | Peter Maydell |
2014-02-20 | target-arm: Remove unused ARMCPUState sr substruct | Peter Maydell |
2014-02-20 | target-arm: Restrict check_ap() use of S and R bits to v6 and earlier | Peter Maydell |
2014-02-20 | target-arm: Define names for SCTLR bits | Peter Maydell |
2014-02-20 | target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs | Peter Maydell |
2014-02-20 | target-arm: A64: Implement remaining 3-same instructions | Peter Maydell |
2014-02-20 | target-arm: A64: Implement floating point pairwise insns | Alex Bennée |
2014-02-20 | target-arm: A64: Implement SIMD FP compare and set insns | Alex Bennée |