Age | Commit message (Expand) | Author |
2015-10-07 | tcg: Pass data argument to restore_state_to_opc | Richard Henderson |
2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson |
2015-10-07 | target-*: Drop cpu_gen_code define | Richard Henderson |
2015-10-07 | target-arm: Add condexec state to insn_start | Richard Henderson |
2015-10-07 | target-*: Introduce and use cpu_breakpoint_test | Richard Henderson |
2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson |
2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson |
2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson |
2015-09-25 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
2015-09-25 | arm: clarify the use of muldiv64() | Laurent Vivier |
2015-09-25 | arm: Remove ELF_MACHINE from cpu.h | Peter Crosthwaite |
2015-09-24 | hw/intc: Initial implementation of vGICv3 | Pavel Fedin |
2015-09-24 | arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create() | Pavel Fedin |
2015-09-15 | target-arm: Use new revbit functions | Richard Henderson |
2015-09-14 | target-arm: Add VMPIDR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Break out mpidr_read_val() | Edgar E. Iglesias |
2015-09-14 | target-arm: Add VPIDR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Suppress EPD for S2, EL2 and EL3 translations | Edgar E. Iglesias |
2015-09-14 | target-arm: Suppress TBI for S2 translations | Edgar E. Iglesias |
2015-09-14 | target-arm: Add VTTBR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Add VTCR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Use tcg_gen_extrh_i64_i32 | Richard Henderson |
2015-09-14 | target-arm: Recognize ROR | Richard Henderson |
2015-09-14 | target-arm: Eliminate unnecessary zero-extend in disas_bitfield | Richard Henderson |
2015-09-14 | target-arm: Recognize UXTB, UXTH, LSR, LSL | Richard Henderson |
2015-09-14 | target-arm: Recognize SXTB, SXTH, SXTW, ASR | Richard Henderson |
2015-09-14 | target-arm: Implement fcsel with movcond | Richard Henderson |
2015-09-14 | target-arm: Implement ccmp branchless | Richard Henderson |
2015-09-14 | target-arm: Use setcond and movcond for csel | Richard Henderson |
2015-09-14 | target-arm: Handle always condition codes within arm_test_cc | Richard Henderson |
2015-09-14 | target-arm: Introduce DisasCompare | Richard Henderson |
2015-09-14 | target-arm: Share all common TCG temporaries | Richard Henderson |
2015-09-11 | tlb: Add "ifetch" argument to cpu_mmu_index() | Benjamin Herrenschmidt |
2015-09-11 | typofixes - v4 | Veres Lajos |
2015-09-11 | maint: remove / fix many doubled words | Daniel P. Berrange |
2015-09-08 | target-arm: Add AArch64 access to PAR_EL1 | Edgar E. Iglesias |
2015-09-08 | target-arm: Correct opc1 for AT_S12Exx | Edgar E. Iglesias |
2015-09-08 | target-arm: Log the target EL when taking exceptions | Edgar E. Iglesias |
2015-09-08 | target-arm: Fix default_exception_el() function for the case when EL3 is not ... | Sergey Sorokin |
2015-09-07 | target-arm: Refactor CPU affinity handling | Pavel Fedin |
2015-09-07 | target-arm: Fix arm_excp_unmasked() function | Sergey Sorokin |
2015-09-07 | target-arm: Fix AArch32:AArch64 general-purpose register mapping | Sergey Sorokin |
2015-09-07 | arm: Remove hw_error() usages. | Peter Crosthwaite |
2015-09-07 | arm: cpu: assert() on no-EL2 virt IRQ error condition. | Peter Crosthwaite |
2015-09-07 | target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction | Peter Maydell |
2015-09-07 | target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block | Peter Maydell |
2015-09-07 | target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call | Peter Maydell |
2015-09-07 | target-arm/arm-semi.c: Support widening APIs to 64 bits | Peter Maydell |
2015-09-07 | target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' | Peter Maydell |
2015-09-07 | target-arm: Improve semihosting debug prints | Christopher Covington |