Age | Commit message (Expand) | Author |
2014-09-25 | target-arm: Use cpu_exec_interrupt qom hook | Richard Henderson |
2014-09-12 | target-arm: Make *IS TLB maintenance ops affect all CPUs | Peter Maydell |
2014-09-12 | target-arm: Push legacy wildcard TLB ops back into v6 | Peter Maydell |
2014-09-12 | target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 | Peter Maydell |
2014-09-12 | target-arm: Remove comment about MDSCR_EL1 being dummy implementation | Peter Maydell |
2014-09-12 | target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 | Peter Maydell |
2014-09-12 | target-arm: Implement handling of fired watchpoints | Peter Maydell |
2014-09-12 | target-arm: Move extended_addresses_enabled() to internals.h | Peter Maydell |
2014-09-12 | target-arm: Implement setting of watchpoints | Peter Maydell |
2014-09-12 | target-arm: Fix broken indentation in arm_cpu_reest() | Martin Galvan |
2014-09-12 | target-arm: Fix resetting issues on ARMv7-M CPUs | Martin Galvan |
2014-08-29 | target-arm: Implement pmccfiltr_write function | Alistair Francis |
2014-08-29 | target-arm: Remove old code and replace with new functions | Alistair Francis |
2014-08-29 | target-arm: Implement pmccntr_sync function | Alistair Francis |
2014-08-29 | target-arm: Add arm_ccnt_enabled function | Alistair Francis |
2014-08-29 | target-arm: Implement PMCCNTR_EL0 and related registers | Alistair Francis |
2014-08-29 | arm: Implement PMCCNTR 32b read-modify-write | Peter Crosthwaite |
2014-08-29 | target-arm: Make the ARM PMCCNTR register 64-bit | Alistair Francis |
2014-08-29 | target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values | Peter Maydell |
2014-08-29 | target-arm: Fix regression that disabled VFP for ARMv5 CPUs | Peter Maydell |
2014-08-19 | arm: cortex-a9: Fix cache-line size and associativity | Peter Crosthwaite |
2014-08-19 | arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 | Christoffer Dall |
2014-08-19 | target-arm: Rename QEMU PSCI v0.1 definitions | Christoffer Dall |
2014-08-19 | target-arm: Implement MDSCR_EL1 as having state | Peter Maydell |
2014-08-19 | target-arm: Implement ARMv8 single-stepping for AArch32 code | Peter Maydell |
2014-08-19 | target-arm: Implement ARMv8 single-step handling for A64 code | Peter Maydell |
2014-08-19 | target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb | Peter Maydell |
2014-08-19 | target-arm: Set PSTATE.SS correctly on exception return from AArch64 | Peter Maydell |
2014-08-19 | target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 | Peter Maydell |
2014-08-19 | target-arm: Don't allow AArch32 to access RES0 CPSR bits | Peter Maydell |
2014-08-19 | target-arm: Adjust debug ID registers per-CPU | Peter Maydell |
2014-08-19 | target-arm: Provide both 32 and 64 bit versions of debug registers | Peter Maydell |
2014-08-19 | target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 | Peter Maydell |
2014-08-19 | target-arm: Collect up the debug cp register definitions | Peter Maydell |
2014-08-19 | target-arm: Fix return address for A64 BRK instructions | Peter Maydell |
2014-08-12 | trace: [tcg] Include TCG-tracing header on all targets | Lluís Vilanova |
2014-08-04 | target-arm: A64: fix TLB flush instructions | Alex Bennée |
2014-08-04 | target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault | Alex Bennée |
2014-08-04 | target-arm: Fix bit test in sp_el0_access | Stefan Weil |
2014-08-04 | target-arm: Add FAR_EL2 and 3 | Edgar E. Iglesias |
2014-08-04 | target-arm: Add ESR_EL2 and 3 | Edgar E. Iglesias |
2014-08-04 | target-arm: Make far_el1 an array | Edgar E. Iglesias |
2014-08-04 | target-arm: A64: Respect SPSEL when taking exceptions | Edgar E. Iglesias |
2014-08-04 | target-arm: A64: Respect SPSEL in ERET SP restore | Edgar E. Iglesias |
2014-08-04 | target-arm: A64: Break out aarch64_save/restore_sp | Edgar E. Iglesias |
2014-07-08 | target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs | Peter Maydell |
2014-06-24 | Fix new typos (found by codespell) | Stefan Weil |
2014-06-19 | target-arm: Introduce per-CPU field for PSCI version | Pranavkumar Sawargaonkar |
2014-06-19 | target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64 | Pranavkumar Sawargaonkar |
2014-06-19 | target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible | Pranavkumar Sawargaonkar |