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2011-07-30exec.h cleanupBlue Swirl
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-23Correct spelling of licensedMatthew Fernandez
Correct typos of "licenced" to "licensed". Reviewed-by: Stefan Weil <weil@mail.berlios.de> Reviewed-by: Andreas F=E4rber <andreas.faerber@web.de> Signed-off-by: Matthew Fernandez <matthew.fernandez@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-07-20Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-armBlue Swirl
* 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK access target-arm: Minimal implementation of performance counters Revert "Makefile.target: Allow target helpers to be in any *_helper.c file" Revert "target-arm: Use global env in neon_helper.c helpers" target-arm: Pass fp status pointer explicitly to neon fp helpers target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState target-arm: Add helper function to generate code to get fpstatus pointer Revert "target-arm: Use global env in iwmmxt_helper.c helpers" Conflicts: Makefile.target
2011-07-04arm: Add const attribute to some arm_boot_info pointersStefan Weil
Parameter 'info' is const, so add the missing attribute. v2: Add 'const' to the local variable info in do_cpu_reset() and to the boot_info field in CPUARMState (suggested by Peter Maydell). Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-06-26Remove exec-all.h include directivesBlue Swirl
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl
Before the next patch, fix coding style of the areas affected. Change the type of the return value from cpu_has_work() and qemu_cpu_has_work() to bool. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu_loop_exit: avoid using AREG0Blue Swirl
Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-22target-arm: Fix BASEPRI, BASEPRI_MAX, and FAULTMASK accessSebastian Huber
Correct the decode of the register numbers for BASEPRI, BASEPRI_MAX and FAULTMASK, according to "ARMv7-M Architecture Reference Manual" issue D section "B5.2.3 MRS" and "B5.2.3 MSR". Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Minimal implementation of performance countersPeter Maydell
Newer Linux kernels assume the existence of the performance counter cp15 registers. Provide a minimal implementation of these registers. We support no events. This should be compliant with the ARM ARM, except that we don't implement the cycle counter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22Revert "target-arm: Use global env in neon_helper.c helpers"Peter Maydell
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3 so that we return to passing CPUState to helpers as an explicit parameter. (There were a number of conflicts in target-arm/translate.c which had to be resolved by hand so it is not a pure revert.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Pass fp status pointer explicitly to neon fp helpersPeter Maydell
Make the Neon helpers for various floating point operations take an explicit pointer to the float_status they use, so they don't rely on the global environment pointer any more. This also allows us to drop the mul/sub/add helpers completely and just use the vfp versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUStatePeter Maydell
Make the VFP binop helper functions take a pointer to the fp status, not the entire CPUState. This will allow us to use them for Neon operations too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22target-arm: Add helper function to generate code to get fpstatus pointerPeter Maydell
Add and use a helper function which returns a TCGv which is a pointer to the fp_status for either Neon or VFP operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-22Revert "target-arm: Use global env in iwmmxt_helper.c helpers"Peter Maydell
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79, returning the iwmmxt helpers to passing env in as a parameter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-06-03target-arm: BKPT instructions should raise prefetch aborts with IFSR type 00010Alex Zuepke
Signed-off-by: Alex Zuepke <azuepke@sysgo.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-06-03target-arm: Fix compilation failure for 64 bit hostsPeter Maydell
Use the correct _ptr aliases for manipulating the pointer to the fp_status; this fixes a compilation failure on 64 bit hosts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23target-arm/exec.h: Remove unused #define of M0Peter Maydell
Remove a preprocessor #define which is never used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23target-arm: Signal InvalidOp for Neon GE and GT compares of QNaNPeter Maydell
If the input to a Neon float comparison is a quiet NaN, the ARM ARM specifies that we should raise InvalidOp if the comparison is GE or GT but not for EQ. (Signaling NaNs raise InvalidOp regardless). This means only EQ should use the _quiet version of the comparison function. We implement this by cleaning up the comparison helpers to call the appopriate versions of the softfloat simple comparison functions (float32_le and friends) rather than the generic float32_compare functions. This makes them simple enough that they are clearer opencoded rather than macroised. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23target-arm: Use correct float status for Neon int-float conversionsPeter Maydell
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helper functions take a pointer to the appropriate float_status value rather than simply taking a pointer to the entire CPUState, and making translate.c pass a pointer to vfp.fp_status or vfp.standard_fp_status appropriately for whether the instruction being translated is Neon or VFP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23target-arm: Signal Underflow when denormal flushed to zero on outputPeter Maydell
On ARM the architecture mandates that when an output denormal is flushed to zero we must set the FPSCR UFC (underflow) bit, so map softfloat's float_flag_output_denormal accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23target-arm: Signal InputDenormal for VRECPE, VRSQRTE, VRECPS, VRSQRTSPeter Maydell
The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormals as special cases, so we must set the InputDenormal exception flag ourselves. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-23target-arm: Don't set FP exceptions in recip, recip_sqrt estimate fnsPeter Maydell
The functions which do the core estimation algorithms for the VRSQRTE and VRECPE instructions should not set floating point exception flags, so use a local fp status for doing these calculations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-15target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNsPeter Maydell
Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires that we implement the set of negations and additions specified by the ARM ARM; plausible looking simplifications like turning (-A + B) into (B - A) or computing (A + B) rather than (B + A) result in selecting the wrong NaN or returning a NaN with the wrong sign bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-12Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori
Conflicts: cpu-all.h
2011-05-08target-arm: Privatize CPU_INTERRUPT_FIQ.Richard Henderson
This interrupt name was only used by the ARM port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-05-08Fix typos in comments and code (occured -> occurred and related)Stefan Weil
The code changed here is an unused data type name (evt_flush_occurred). Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-05-08Fix typos in comments (neccessary -> necessary)Stefan Weil
Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-04-27target-arm: Don't update base register on abort in Thumb T1 LDMPeter Maydell
Make sure the base register isn't updated if it is in the load list for a Thumb LDM (T1 encoding) which aborts partway through the load. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-27target-arm: fix LDMIA bug on page boundaryYuYeon Oh
target-arm: fix LDMIA bug on page boundary When consecutive memory locations are on page boundary, a base register may be loaded before page fault occurs. After page fault handling, it losts the memory location information. To solve this problem, loading a base register has to put back. Signed-off-by: Yuyeon Oh <yuyeon.oh@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-25target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structuresPeter Maydell
Correctly UNDEF for Neon VLD/VST "multiple structures" forms where the align field is not valid. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-25target-arm: Handle UNDEFs for Neon single element load/storesPeter Maydell
Handle the UNDEF and UNPREDICTABLE cases for Neon "single element to one lane" VLD and "single element from one lane" VST. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-20target-arm: Set Invalid flag for NaN in float-to-int conversionsPeter Maydell
When we catch the special case of an input NaN in ARM float to int helper functions, set the Invalid flag as well as returning the correct result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-20Implement basic part of SA-1110/SA-1100Dmitry Eremin-Solenikov
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation. Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the hw/strongarm.c Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-20Remove unused function parameter from cpu_restore_stateStefan Weil
The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil
Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-17move helpers.h to helper.hLluís
This provides a consistent naming scheme across all targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-16Fix some typos in comments and documentationStefan Weil
helpfull -> helpful usefull -> useful cotrol -> control and a grammar fix. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-04-13target-arm: Don't overflow when calculating value for signed VABALPeter Maydell
In the VABAL instruction we take the absolute difference of two values of size x and store it in a result of size 2x. This means we have to be careful to calculate the absolute difference using a wide enough type that we don't accidentally overflow. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Detect tininess before rounding for FP operationsPeter Maydell
The ARM architecture mandates that we detect tininess before rounding, so set the softfloat fp_status up appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for VDUP (scalar)Juha Riihimäki
Handle the UNDEF cases for VDUP(scalar): imm4 == x000 Q == 1 && Vd<0> == 1 Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEFPeter Maydell
Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF it rather than allowing the helper function to index off the end of the register file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for Neon 2 register misc formsPeter Maydell
Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> == 1 || Vm<0> == 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q == 1 || Vm<0> == 1 * VSHLL,VCVT.F32.F16 UNDEF if Q == 1 || Vd<0> == 1 (The only other UNDEF case is VZIP,VUZP if Q == 0 && size == 10, which we already handle.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Simplify checking of size field in Neon 2reg-misc formsPeter Maydell
Many of the Neon "2 register misc" instruction forms require invalid size fields to cause the instruction to UNDEF. Pull this information out into an array; this simplifies the code and also means we can do the check early and avoid the problem of leaking TCG temporaries in the illegal_op case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for VEXTPeter Maydell
VEXT must UNDEF if Q == 1 && (Vd<0> == 1 || Vr<0> == 1 || Vm<0> == 1) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for Neon 2 regs + scalar formsPeter Maydell
Add missing checks for cases which must UNDEF in the Neon "2 registers and a scalar" data processing instruction space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for Neon 3-regs-different-widthsPeter Maydell
Add missing UNDEF checks for instructions in the Neon "3 registers of different widths" data processing space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for Neon invalid modified-immediatesPeter Maydell
For Neon "one register and a modified immediate value" forms, the combination op=1 cmode=1111 is unallocated and should UNDEF. All instructions of this form also UNDEF if Q == 1 and Vd<0> == 1. We also add a comment on the only UNPREDICTABLE in this space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Collapse VSRI case into VSHL, VSLIPeter Maydell
Collapse some switch cases for VSRI into those for VSHL, VSLI, since the bodies are the same. (This is not completely obvious for the size < 3 case, but since for VSRI we know U=1 the GEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded VSHL/VSLI case.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-12target-arm: Handle UNDEF cases for Neon "2 regs and shift" insnsPeter Maydell
Correctly handle all the UNDEF cases for Neon instructions of the "2 registers and shift" form, and make sure that we check for these cases early enough not to leak TCG temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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