Age | Commit message (Expand) | Author |
2015-08-25 | target-arm: Implement AArch64 TLBI operations on IPAs | Peter Maydell |
2015-08-25 | target-arm: Implement missing EL3 TLB invalidate operations | Peter Maydell |
2015-08-25 | target-arm: Implement missing EL2 TLBI operations | Peter Maydell |
2015-08-25 | target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch | Peter Maydell |
2015-08-25 | target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order | Peter Maydell |
2015-08-25 | target-arm: Implement AArch32 ATS1H* operations | Peter Maydell |
2015-08-25 | target-arm: Enable the AArch32 ATS12NSO ops | Peter Maydell |
2015-08-25 | target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 | Peter Maydell |
2015-08-25 | target-arm: Wire up AArch64 EL2 and EL3 address translation ops | Peter Maydell |
2015-08-25 | target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations | Peter Maydell |
2015-08-25 | target-arm: Implement missing ACTLR registers | Peter Maydell |
2015-08-25 | target-arm: Implement missing AFSR registers | Peter Maydell |
2015-08-25 | target-arm: Implement missing AMAIR registers | Peter Maydell |
2015-08-25 | target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers | Peter Maydell |
2015-08-24 | tcg: Remove tcg_gen_trunc_i64_i32 | Richard Henderson |
2015-08-13 | target-arm: Add AArch32 banked register access to secure physical timer | Peter Maydell |
2015-08-13 | target-arm: Add the AArch64 view of the Secure physical timer | Peter Maydell |
2015-08-13 | target-arm: Add debug check for mismatched cpreg resets | Peter Maydell |
2015-08-13 | Introduce gic_class_name() instead of repeating condition | Pavel Fedin |
2015-08-13 | target-arm: Add the Hypervisor timer | Edgar E. Iglesias |
2015-08-13 | target-arm: Pass timeridx as argument to various timer functions | Edgar E. Iglesias |
2015-08-13 | target-arm: Rename and move gt_cnt_reset | Edgar E. Iglesias |
2015-08-13 | target-arm: Add CNTHCTL_EL2 | Edgar E. Iglesias |
2015-08-13 | target-arm: Add CNTVOFF_EL2 | Edgar E. Iglesias |
2015-07-21 | target-arm: kvm: Differentiate registers based on write-back levels | Christoffer Dall |
2015-07-15 | target-arm: Fix broken SCTLR_EL3 reset | Peter Maydell |
2015-07-09 | disas: arm: QOMify target specific disas setup | Peter Crosthwaite |
2015-07-09 | cpu-exec: Purge all uses of ENV_GET_CPU() | Peter Crosthwaite |
2015-07-09 | cpu: Change cpu_exec_init() arg to cpu, not env | Peter Crosthwaite |
2015-07-09 | cpu: Add Error argument to cpu_exec_init() | Bharata B Rao |
2015-07-07 | crypto: move built-in AES implementation into crypto/ | Daniel P. Berrange |
2015-07-06 | target-arm: Implement YIELD insn to yield in ARM and Thumb translators | Peter Maydell |
2015-07-06 | target-arm: Split DISAS_YIELD from DISAS_WFE | Peter Maydell |
2015-07-06 | target-arm: fix write helper for TLBI ALLE1IS | Sergey Fedorov |
2015-06-26 | target-arm: A64: Print ELR when taking exceptions | Soren Brinkmann |
2015-06-26 | target-arm: default empty semihosting cmdline | Liviu Ionescu |
2015-06-22 | Include qapi/qmp/qerror.h exactly where needed | Markus Armbruster |
2015-06-22 | disas: Remove uses of CPU env | Peter Crosthwaite |
2015-06-19 | semihosting: add --semihosting-config arg sub-argument | Leon Alrae |
2015-06-19 | semihosting: create SemihostingConfig structure and semihost.h | Leon Alrae |
2015-06-19 | target-arm: Add support for Cortex-R5 | Peter Crosthwaite |
2015-06-19 | target-arm: Implement PMSAv7 MPU | Peter Crosthwaite |
2015-06-19 | target-arm: Add registers for PMSAv7 | Peter Crosthwaite |
2015-06-19 | target-arm/helper.c: define MPUIR register | Peter Crosthwaite |
2015-06-19 | target-arm: Do not reset sysregs marked as ALIAS | Sergey Fedorov |
2015-06-19 | target-arm: Add the Cortex-M4 CPU | Aurelio C. Remonda |
2015-06-15 | target-arm: Correct "preferred return address" for cpreg access exceptions | Peter Maydell |
2015-06-15 | arm: helper: rename get_phys_addr_mpu | Peter Crosthwaite |
2015-06-15 | arm: Add has-mpu property | Peter Crosthwaite |
2015-06-15 | arm: Implement uniprocessor with MP config | Peter Crosthwaite |