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2013-12-17target-arm/kvm: Split 32 bit only code into its own filePeter Maydell
Split ARM KVM support code which is 32 bit specific out into its own file, which we only compile on 32 bit hosts. This will give us a place to add the 64 bit support code without adding lots of ifdefs to kvm.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
2013-12-17ARM: arm_cpu_reset: make it possible to use high vectors for reset_excAntony Pavlov
If hivecs are being used on reset, the CPU should come out of reset at the hivecs reset vector (0xFFFF0000) Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3afc69c4f58f60aa2bbee7b91574a4eb414b1c23.1387160489.git.peter.crosthwaite@xilinx.com [ PC Changes: * Fixed Grammar error in commit message * Elaborated commit message. ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17ARM: cpu: add "reset_hivecs" propertyAntony Pavlov
Add an ARM CPU property for the reset value of hivecs as it is a board/SoC configurable setting. The existence of the property is conditional on the ARM CPU not being M class. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b04216c6bda4bd163f44a55bba552d0e8267481f.1387160489.git.peter.crosthwaite@xilinx.com [ PC Changes: * Elaborated commit message * refactored to use qdev_property_add_static ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm/cpu: Convert reset CBAR to a propertyPeter Crosthwaite
The reset value of the CP15 CBAR is a vendor (machine) configurable property. If ARM_FEATURE_CBAR is set, add it as a property at post_init time. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2f1eec3f912135deea6252360e03645003d12e0a.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: Define and use ARM_FEATURE_CBARPeter Crosthwaite
Some processors (notably A9 within Highbank) define and use the CP15 configuration base address (CBAR). This is vendor specific so its best implemented as a CPU property (otherwise we would need vendor specific child classes for every ARM implementation). This patch prepares support for converting CBAR reset value to a CPU property by moving the CP registration out of the CPU init fn, as registration will need to happen at realize time to pick up any property updates. The easiest way to do this is via definition of a new ARM_FEATURE to flag the existence of the register. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 9f697ef1e2ee60a3b9ef971a7f3bc3fa6752a9b7.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm/helper.c: Allow cp15.c15 dummy overridePeter Crosthwaite
The cp15.c15 space is implementation defined. Currently there is a dummy placeholder register RAZing it. Allow overriding of this RAZ so implementations of specific registers can take precedence. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: ed1bacec56dae00cb398c798f8240e8e685f949c.1387160489.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel
This adds support for the AESE/AESD/AESMC/AESIMC instructions that are available on some v8 implementations of Aarch32. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1386266078-6976-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: fix TTBCR write maskingSergey Fedorov
Current implementation is not accurate according to ARMv7-AR reference manual. See "B4.1.153 TTBCR, Translation Table Base Control Register, VMSA | TTBCR format when using the Long-descriptor translation table format". When LPAE feature is supported, EAE, bit[31] selects translation descriptor format and, therefore, TTBCR format. Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386657709-23399-1-git-send-email-s.fedorov@samsung.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Use new qemu_ld/st opcodesRichard Henderson
Retain the existing gen_aa32_* inlines, to aid compilation for A64. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1386628626-21627-1-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.Will Newton
This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Message-id: 1386158099-9239-7-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton
This adds support for the ARMv8 floating point VMAXNM and VMINNM instructions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-6-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Implement ARMv8 VSEL instruction.Will Newton
This adds support for the VSEL floating point selection instruction which was added in ARMv8. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-3-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.Will Newton
Floating point is an extension to the instruction set rather than a coprocessor, so call it directly from the ARM and Thumb decode functions. Signed-off-by: Will Newton <will.newton@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1386158099-9239-2-git-send-email-will.newton@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-12-10target-arm: Provide '-cpu host' when running KVMPeter Maydell
Implement '-cpu host' for ARM when we're using KVM, broadly in line with other KVM-supporting architectures. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-11-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Don't hardcode KVM target CPU to be A15Peter Maydell
Instead of assuming that a KVM target CPU must always be a Cortex-A15 and hardcoding this in kvm_arch_init_vcpu(), store the KVM_ARM_TARGET_* value in the ARMCPU class, and use that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-10-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Allow secondary KVM CPUs to be booted via PSCIPeter Maydell
New ARM boards are generally expected to boot their secondary CPUs via the PSCI interface, rather than ad-hoc "loop around in holding pen code" as hw/arm/boot.c implements. In particular this is necessary for mach-virt kernels. For KVM we achieve this by creating the VCPUs with a feature flag marking them as starting in PSCI powered-down state; the guest kernel will then make a PSCI call (implemented in the host kernel) to start the secondaries at an address of its choosing once it has got the primary CPU up. Implement this setting of the feature flag, controlled by a qdev property for ARMCPU, which board code can set if it is a PSCI system. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-7-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Add ARMCPU field for Linux device-tree 'compatible' stringPeter Maydell
Linux requires device tree CPU nodes to include a 'compatible' string describing the CPU. Add a field in the ARMCPU struct for this so that boards which construct a device tree can insert the correct CPU nodes. Note that there is currently no officially specified 'compatible' string for the TI925T, Cortex-M3 or SA1110 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-6-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Provide PSCI constants to generic QEMU codePeter Maydell
Provide versions of the KVM PSCI constants to non-KVM code; this will allow us to avoid an ifdef in boards which set up a PSCI node in the device tree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-5-git-send-email-peter.maydell@linaro.org
2013-12-10target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVMPeter Maydell
There are a number of places where it would be convenient for ARM code to have working definitions of KVM constants even in code which is compiled with CONFIG_KVM not set. In this situation we can't simply include the kernel KVM headers (which might conflict with host header definitions or not even compile on the compiler we're using) so we have to redefine equivalent constants. Provide a mechanism for doing this and checking that the values match, and use it for the constants we're currently exposing via an ad-hoc mechanism. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1385140638-10444-2-git-send-email-peter.maydell@linaro.org
2013-10-31target-arm: fix sorting issue of KVM cpreg listAlvise Rigo
The compare_u64 function was not sorting the KVM cpreg_list in the right way due to the wrong returned value. Since we are comparing two 64bit values we can't simply return their difference if the returned type is int. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1381513125-26802-2-git-send-email-a.rigo@virtualopensystems.com [PMM: fixed coding style, indent and commit message formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-31target-arm: sort TCG cpreg list by KVM-style 64 bit ID numberAlvise Rigo
Both KVM and TCG populate the cpreg_list with 64 bit register IDs, but in the TCG side the cpreg_list is sorted using the 32 bit ID version while in the kvm side the 64 bit ID version is used. This patch makes the sorting of the cpreg_list consistent between KVM and TCG. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1381513125-26802-1-git-send-email-a.rigo@virtualopensystems.com [PMM: fixed indent, coding style and commit message formatting] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-31target-arm: Add CP15 VBAR supportNathan Rossi
Added Vector Base Address remapping on ARM v7. Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: removed spurious mask of value with 1<<31] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-10-18Merge remote-tracking branch 'bonzini/configure' into stagingAnthony Liguori
# By Peter Maydell (3) and Ákos Kovács (2) # Via Paolo Bonzini * bonzini/configure: ui/Makefile.objs: delete unnecessary cocoa.o dependency default-configs/: CONFIG_GDBSTUB_XML removed Makefile.target: CONFIG_NO_* variables removed rules.mak: New string testing functions rules.mak: New logical functions for handling y/n values
2013-10-16Makefile.target: CONFIG_NO_* variables removedÁkos Kovács
CONFIG_NO_* variables replaced with the lnot logical function Signed-off-by: Ákos Kovács <akoskovacs@gmx.com> [PMM: fixed a few CONFIG_NO_* uses that were missed] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2013-10-11Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori
# By Richard Henderson # Via Richard Henderson * rth/tcg-pull: exec: Add both big- and little-endian memory helpers tcg: Add qemu_ld_st_i32/64 tcg: Add TCGMemOp configure: Remove CONFIG_QEMU_LDST_OPTIMIZATION tcg: Add tcg-be-ldst.h tcg: Add tcg-be-null.h exec: Delete is_tcg_gen_code and GETRA_EXT tcg-aarch64: Update to helper_ret_*_mmu routines tcg: Merge tcg_register_helper into tcg_context_init tcg: Add tcg-runtime.c helpers to all_helpers tcg: Put target helper data into an array. tcg: Remove stray semi-colons from target-*/helper.h tcg: Move helper registration into tcg_context_init target-m68k: Rename helpers.h to helper.h tcg: Use a GHashTable for tcg_find_helper tcg: Delete tcg_helper_get_name declaration tcg-hppa: Remove tcg backend Message-id: 1381440525-6666-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-10-10Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into stagingAnthony Liguori
QOM CPUState refactorings / X86CPU * Fix for X86CPU model field of qemu32/qemu64 CPU models * Bug fix for longjmp on FreeBSD * Removal of unused function * Confinement of clone syscall infrastructure to linux-user # gpg: Signature made Wed 09 Oct 2013 03:40:51 AM PDT using RSA key ID 3E7E013F # gpg: Can't check signature: public key not found # By Andreas Färber (2) and others # Via Andreas Färber * afaerber/tags/qom-cpu-for-anthony: cpu: Drop cpu_model_str from CPU_COMMON cpu: Move cpu_copy() into linux-user cputlb: Remove dead function tlb_update_dirty() cpu-exec: Also reload CPUClass *cc after longjmp return in cpu_exec() target-i386: Set model=6 on qemu64 & qemu32 CPU models
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson
No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-10-07cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber
Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-09-25misc: Use new rotate functionsStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de>
2013-09-10target-arm: Add AArch64 gdbstub supportAlexander Graf
We want to be able to debug AArch64 guests. So let's add the respective gdb stub functions and xml descriptions that allow us to do so. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-12-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org [PMM: dropped unused fp regs XML for now; moved 64 bit only functions to new gdbstub64.c; these are hooked up in AArch64CPU, not via ifdefs in ARMCPU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Add AArch64 translation stubAlexander Graf
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode, registers look vastly different, instruction encoding is completely different, basically the system turns into a different machine. So let's do a simple if() in translate.c to decide whether we can handle the current code in the legacy AArch32 code or in the new AArch64 code. So far, the translation always complains about unallocated instructions. There is no emulator functionality in this patch! Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org [PMM: * provide no-op versions of a64 functions ifndef TARGET_AARCH64; this lets us avoid #ifdefs in translate.c * insert the missing call to disas_a64_insn() * stash the insn in the DisasContext rather than reloading it in real_unallocated_encoding() ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Prepare translation for AArch64 codeAlexander Graf
This patch adds all the prerequisites for AArch64 support that didn't fit into split up patches. It extends important bits in the core cpu headers to also take AArch64 mode into account. Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org [PMM: * rearranged tbflags so AArch64? is bit 31 and if it is set then 30..0 are freely available for whatever makes most sense for that mode * added version bump since we change VFP migration state * added a comment about how VFP/Neon register state works * physical address space is 48 bits, not 64 * added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Disable 32 bit CPUs in 64 bit linux-user buildsPeter Maydell
If we're building aarch64-linux-user then the 32 bit CPUs are all unwanted, because they can't possibly execute the 64 bit binaries we will be running; disable them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-9-git-send-email-peter.maydell@linaro.org
2013-09-10target-arm: Add new AArch64CPUInfo base class and subclassesPeter Maydell
Create a new AArch64CPU class; all 64-bit capable ARM CPUs are subclasses of this. (Currently we only support one, the "any" CPU used by linux-user.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-8-git-send-email-peter.maydell@linaro.org
2013-09-10target-arm: Pass DisasContext* to gen_set_pc_im()Peter Maydell
We want gen_set_pc_im() to work for both AArch64 and AArch32, but to do this we'll need the DisasContext* so we can tell which mode we're in, so pass it in as a parameter. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-7-git-send-email-peter.maydell@linaro.org
2013-09-10target-arm: Fix target_ulong/uint32_t confusionsAlexander Graf
Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-6-git-send-email-peter.maydell@linaro.org [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Export cpu_envAlexander Graf
The cpu_env tcg variable will be used by both the AArch32 and AArch64 handling code. Unstaticify it, so that both sides can make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-5-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Extract the disas struct to a header fileAlexander Graf
We will need to share the disassembly status struct between AArch32 and AArch64 modes. So put it into a header file that both sides can use. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-4-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Abstract out load/store from a vaddr in AArch32Peter Maydell
AArch32 code (ie traditional 32 bit world) expects to be able to pass a vaddr in a TCGv_i32. However when QEMU is compiled with TARGET_LONG_BITS=32 the TCG load/store functions take a TCGv_i64. Abstract out load/store with a 32 bit vaddr so we have a place to put the zero extension of the vaddr and the extension/truncation of the data value. Apart from the function definitions most of this patch is a simple s/tcg_gen_qemu_/gen_aa32_/. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org
2013-09-10target-arm: Implement qmp query-cpu-definitionsCole Robinson
Libvirt uses this to introspect available CPU models. Signed-off-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: c0bdcd6c7ea6a085a6902ccaa73180fd771c8267.1378303555.git.crobinso@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: fix ARMv7M stack alignment on resetSebastian Ottlik
When the initial SP is loaded from the vector table on ARMv7M systems the two least significant bits are ignored as the stack is always aligned at a four byte boundary (see ARM DDI 0403C, B1.4.1 and B1.5.5). So far QEMU did not ignore these bits leading to a stack alignment inconsitent with real hardware for binaries that rely on this behaviour. This patch fixes this issue by masking the two least significant bits when loading the SP. Signed-off-by: Sebastian Ottlik <ottlik@fzi.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1378286595-27072-1-git-send-email-ottlik@fzi.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-09-10target-arm: Avoid "1 << 31" undefined behaviourPeter Maydell
Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. For consistency, we make all the CPSR_* constants unsigned, though the only one which triggers undefined behaviour is CPSR_N. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org
2013-09-10target-arm: Use sextract32() in branch decodePeter Maydell
In the decode of ARM B and BL insns, swap the order of the "append 2 implicit zeros to imm24" and the sign extend, and use the new sextract32() utility function to do the latter. This avoids a direct dependency on the undefined C behaviour of shifting into the sign bit of an integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1378391908-22137-2-git-send-email-peter.maydell@linaro.org
2013-09-10target-arm: Make '-cpu any' available in linux-user mode onlyPeter Maydell
Make the 'any' CPU for target-arm available only in linux-user mode. The ARM target provides a CPU named "any", which turns on support for all user-level instruction set extensions we know about. This is intended for linux-user emulation mode, where it is the default CPU type. It makes no sense to try to use this for system emulation, since we don't initialize it with any system-level information like feature register values or implementation specific cp15 registers. (Unsurprisingly, some boards won't boot at all, though you might get lucky in some cases where the guest doesn't happen to prod things that aren't there.) Prevent users from making this command line error by removing the CPU definition from the softmmu build. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de> Message-id: 1378213995-12945-1-git-send-email-peter.maydell@linaro.org
2013-09-03Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori
# By Stefan Weil (6) and others # Via Michael Tokarev * mjt/trivial-patches: aio / timers: use g_usleep() not sleep() adlib: sort offsets in portio registration qmp: fix integer usage in examples tci: Remove function tcg_out64 (fix broken build) target-arm: Report unimplemented opcodes (LOG_UNIMP) pflash_cfi02.c: fix debug macro configure: Remove unneeded redirections of stderr (pkg-config --exists) configure: Remove unneeded redirections of stderr (pkg-config --cflags, --libs) configure: Don't write .pyc files by default (python -B) curl: qemu_bh_new() can never return NULL slirp/arp_table.c: Avoid shifting into sign bit of signed integers configure: disable clang -Wstring-plus-int warning rdma: silly ipv6 bugfix misc: Fix some typos in names and comments slirp: Port redirection option behave differently on Linux and Windows Message-id: 1378119695-14568-1-git-send-email-mjt@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson
And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-01target-arm: Report unimplemented opcodes (LOG_UNIMP)Stefan Weil
These unimplemented opcodes are handled like illegal opcodes, but they are used in existing code. We should at least report when they are executed. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-08-22aio / timers: Switch entire codebase to the new timer APIAlex Bligh
This is an autogenerated patch using scripts/switch-timer-api. Switch the entire code base to using the new timer API. Note this patch may introduce some line length issues. Signed-off-by: Alex Bligh <alex@alex.org.uk> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2013-08-20target-arm: Implement the generic timerPeter Maydell
The ARMv7 architecture specifies a 'generic timer' which is implemented via cp15 registers. Newer kernels will prefer to use this rather than a devboard-level timer. Implement the generic timer for TCG; for KVM we will already use the hardware's virtualized timer for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1376065080-26661-4-git-send-email-peter.maydell@linaro.org
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-18 21:01:39 +0000