Age | Commit message (Expand) | Author |
2014-12-22 | target-arm: add cpu feature EL3 to CPUs with Security Extensions | Fabian Aggeler |
2014-12-22 | target-arm: Add ARMCPU secure property | Greg Bellows |
2014-12-22 | target-arm: Add feature unset function | Greg Bellows |
2014-12-22 | target-arm: Merge EL3 CP15 register lists | Greg Bellows |
2014-12-11 | target-arm: Check error conditions on kvm_arm_reset_vcpu | Christoffer Dall |
2014-12-11 | target-arm: Support save/load for 64 bit CPUs | Peter Maydell |
2014-12-11 | target-arm/kvm: make reg sync code common between kvm32/64 | Alex Bennée |
2014-12-11 | target-arm: make MAIR0/1 banked | Greg Bellows |
2014-12-11 | target-arm: make c13 cp regs banked (FCSEIDR, ...) | Fabian Aggeler |
2014-12-11 | target-arm: make VBAR banked | Greg Bellows |
2014-12-11 | target-arm: make PAR banked | Fabian Aggeler |
2014-12-11 | target-arm: make IFAR/DFAR banked | Fabian Aggeler |
2014-12-11 | target-arm: make DFSR banked | Fabian Aggeler |
2014-12-11 | target-arm: make IFSR banked | Fabian Aggeler |
2014-12-11 | target-arm: make DACR banked | Fabian Aggeler |
2014-12-11 | target-arm: make TTBCR banked | Fabian Aggeler |
2014-12-11 | target-arm: make TTBR0/1 banked | Fabian Aggeler |
2014-12-11 | target-arm: make CSSELR banked | Fabian Aggeler |
2014-12-11 | target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI | Fabian Aggeler |
2014-12-11 | target-arm: add SCTLR_EL3 and make SCTLR banked | Fabian Aggeler |
2014-12-11 | target-arm: add MVBAR support | Fabian Aggeler |
2014-12-11 | target-arm: add SDER definition | Greg Bellows |
2014-12-11 | target-arm: add NSACR register | Fabian Aggeler |
2014-12-11 | target-arm: implement IRQ/FIQ routing to Monitor mode | Fabian Aggeler |
2014-12-11 | target-arm: move AArch32 SCR into security reglist | Fabian Aggeler |
2014-12-11 | target-arm: insert AArch32 cpregs twice into hashtable | Fabian Aggeler |
2014-12-11 | target-arm: add secure state bit to CPREG hash | Peter Maydell |
2014-12-11 | target-arm: add CPREG secure state support | Fabian Aggeler |
2014-12-11 | target-arm: add non-secure Translation Block flag | Sergey Fedorov |
2014-12-11 | target-arm: add banked register accessors | Fabian Aggeler |
2014-12-11 | target-arm: add async excp target_el function | Greg Bellows |
2014-12-11 | target-arm: extend async excp masking | Greg Bellows |
2014-12-11 | Pass semihosting exit code back to system. | Liviu Ionescu |
2014-11-17 | target-arm: handle address translations that start at level 3 | Peter Maydell |
2014-11-04 | target-arm: Correct condition for taking VIRQ and VFIQ | Peter Maydell |
2014-11-04 | target-arm: Separate out M profile cpu_exec_interrupt handling | Peter Maydell |
2014-11-04 | target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() | Peter Maydell |
2014-11-04 | target-arm/translate.c: Don't pass CPUARMState around in the decoder | Peter Maydell |
2014-11-04 | target-arm/translate.c: Don't use IS_M() | Peter Maydell |
2014-11-04 | target-arm/translate.c: Use arm_dc_feature() rather than arm_feature() | Peter Maydell |
2014-11-04 | target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macros | Peter Maydell |
2014-11-02 | target-arm: A64: remove redundant store | Alex Bennée |
2014-10-24 | target-arm: A32: Emulate the SMC instruction | Fabian Aggeler |
2014-10-24 | target-arm: make arm_current_el() return EL3 | Fabian Aggeler |
2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows |
2014-10-24 | target-arm: reject switching to monitor mode | Sergey Fedorov |
2014-10-24 | target-arm: add arm_is_secure() function | Fabian Aggeler |
2014-10-24 | target-arm: increase arrays of registers R13 & R14 | Fabian Aggeler |
2014-10-24 | target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 | Peter Maydell |
2014-10-24 | target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" | Peter Maydell |