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AgeCommit message (Expand)Author
2015-02-05Fix FMULX not squashing denormalized inputs when FZ is set.Xiangyu Hu
2015-02-05target-arm: Add checks that cpreg raw accesses are handledPeter Maydell
2015-02-05target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell
2015-02-05target-arm: Add missing SP_ELx register definitionGreg Bellows
2015-02-05target-arm: Change reset to highest available ELGreg Bellows
2015-02-05target-arm: Add extended RVBAR supportGreg Bellows
2015-02-05target-arm: Fix RVBAR_EL1 register encodingGreg Bellows
2015-01-26vmstate: accept QEMUTimer in VMSTATE_TIMER*, add VMSTATE_TIMER_PTR*Paolo Bonzini
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell
2015-01-16target-arm: crypto: fix BE host supportArd Biesheuvel
2015-01-15target-arm: Fix typo in comment (seperately -> separately)Stefan Weil
2015-01-12kvm: extend kvm_irqchip_add_msi_route to work on s390Frank Blaschka
2015-01-09Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini
2014-12-22target-arm: add cpu feature EL3 to CPUs with Security ExtensionsFabian Aggeler
2014-12-22target-arm: Add ARMCPU secure propertyGreg Bellows
2014-12-22target-arm: Add feature unset functionGreg Bellows
2014-12-22target-arm: Merge EL3 CP15 register listsGreg Bellows
2014-12-11target-arm: Check error conditions on kvm_arm_reset_vcpuChristoffer Dall
2014-12-11target-arm: Support save/load for 64 bit CPUsPeter Maydell
2014-12-11target-arm/kvm: make reg sync code common between kvm32/64Alex Bennée
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler
2014-12-11target-arm: make VBAR bankedGreg Bellows
2014-12-11target-arm: make PAR bankedFabian Aggeler
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler
2014-12-11target-arm: make DFSR bankedFabian Aggeler
2014-12-11target-arm: make IFSR bankedFabian Aggeler
2014-12-11target-arm: make DACR bankedFabian Aggeler
2014-12-11target-arm: make TTBCR bankedFabian Aggeler
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler
2014-12-11target-arm: make CSSELR bankedFabian Aggeler
2014-12-11target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler
2014-12-11target-arm: add MVBAR supportFabian Aggeler
2014-12-11target-arm: add SDER definitionGreg Bellows
2014-12-11target-arm: add NSACR registerFabian Aggeler
2014-12-11target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler
2014-12-11target-arm: move AArch32 SCR into security reglistFabian Aggeler
2014-12-11target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov
2014-12-11target-arm: add banked register accessorsFabian Aggeler
2014-12-11target-arm: add async excp target_el functionGreg Bellows
2014-12-11target-arm: extend async excp maskingGreg Bellows
2014-12-11Pass semihosting exit code back to system.Liviu Ionescu
2014-11-17target-arm: handle address translations that start at level 3Peter Maydell
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell
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