Age | Commit message (Expand) | Author |
2014-11-04 | target-arm: Correct condition for taking VIRQ and VFIQ | Peter Maydell |
2014-11-04 | target-arm: Separate out M profile cpu_exec_interrupt handling | Peter Maydell |
2014-11-04 | target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() | Peter Maydell |
2014-11-04 | target-arm/translate.c: Don't pass CPUARMState around in the decoder | Peter Maydell |
2014-11-04 | target-arm/translate.c: Don't use IS_M() | Peter Maydell |
2014-11-04 | target-arm/translate.c: Use arm_dc_feature() rather than arm_feature() | Peter Maydell |
2014-11-04 | target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macros | Peter Maydell |
2014-11-02 | target-arm: A64: remove redundant store | Alex Bennée |
2014-10-24 | target-arm: A32: Emulate the SMC instruction | Fabian Aggeler |
2014-10-24 | target-arm: make arm_current_el() return EL3 | Fabian Aggeler |
2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows |
2014-10-24 | target-arm: reject switching to monitor mode | Sergey Fedorov |
2014-10-24 | target-arm: add arm_is_secure() function | Fabian Aggeler |
2014-10-24 | target-arm: increase arrays of registers R13 & R14 | Fabian Aggeler |
2014-10-24 | target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 | Peter Maydell |
2014-10-24 | target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" | Peter Maydell |
2014-10-24 | target-arm: Correct sense of the DCZID DZP bit | Peter Maydell |
2014-10-24 | target-arm: add emulation of PSCI calls for system emulation | Rob Herring |
2014-10-24 | target-arm: Add support for A32 and T32 HVC and SMC insns | Peter Maydell |
2014-10-24 | target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers | Peter Maydell |
2014-10-24 | target-arm: add missing PSCI constants needed for PSCI emulation | Ard Biesheuvel |
2014-10-24 | target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes | Rob Herring |
2014-10-24 | target-arm: add powered off cpu state | Rob Herring |
2014-10-06 | gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag | Peter Maydell |
2014-09-29 | target-arm: Add support for VIRQ and VFIQ | Edgar E. Iglesias |
2014-09-29 | target-arm: Add IRQ and FIQ routing to EL2 and 3 | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the SMC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: Add a Hypervisor Trap exception type | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the HVC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Correct updates to FAR and ESR on exceptions | Edgar E. Iglesias |
2014-09-29 | target-arm: Don't take interrupts targeting lower ELs | Edgar E. Iglesias |
2014-09-29 | target-arm: Break out exception masking to a separate func | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Refactor aarch64_cpu_do_interrupt | Edgar E. Iglesias |
2014-09-29 | target-arm: Add SCR_EL3 | Edgar E. Iglesias |
2014-09-29 | target-arm: Add HCR_EL2 | Edgar E. Iglesias |
2014-09-29 | target-arm: Don't handle c15_cpar changes via tb_flush() | Peter Maydell |
2014-09-29 | target-arm: Implement handling of breakpoint firing | Peter Maydell |
2014-09-29 | target-arm: Implement setting guest breakpoints | Peter Maydell |
2014-09-25 | target-arm: Use cpu_exec_interrupt qom hook | Richard Henderson |
2014-09-12 | target-arm: Make *IS TLB maintenance ops affect all CPUs | Peter Maydell |
2014-09-12 | target-arm: Push legacy wildcard TLB ops back into v6 | Peter Maydell |
2014-09-12 | target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 | Peter Maydell |
2014-09-12 | target-arm: Remove comment about MDSCR_EL1 being dummy implementation | Peter Maydell |
2014-09-12 | target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 | Peter Maydell |
2014-09-12 | target-arm: Implement handling of fired watchpoints | Peter Maydell |
2014-09-12 | target-arm: Move extended_addresses_enabled() to internals.h | Peter Maydell |
2014-09-12 | target-arm: Implement setting of watchpoints | Peter Maydell |
2014-09-12 | target-arm: Fix broken indentation in arm_cpu_reest() | Martin Galvan |
2014-09-12 | target-arm: Fix resetting issues on ARMv7-M CPUs | Martin Galvan |
2014-08-29 | target-arm: Implement pmccfiltr_write function | Alistair Francis |