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AgeCommit message (Expand)Author
2014-02-20target-arm: Remove unused ARMCPUState sr substructPeter Maydell
2014-02-20target-arm: Restrict check_ap() use of S and R bits to v6 and earlierPeter Maydell
2014-02-20target-arm: Define names for SCTLR bitsPeter Maydell
2014-02-20target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUsPeter Maydell
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell
2014-02-20target-arm: A64: Implement floating point pairwise insnsAlex Bennée
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée
2014-02-20target-arm: A64: Implement scalar three different instructionsPeter Maydell
2014-02-20target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell
2014-02-20target-arm: A64: Implement long vector x indexed insnsPeter Maydell
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell
2014-02-11exec: Make stl_*_phys input an AddressSpaceEdgar E. Iglesias
2014-02-11exec: Make ldq/ldub_*_phys input an AddressSpaceEdgar E. Iglesias
2014-02-11exec: Make ldl_*_phys input an AddressSpaceEdgar E. Iglesias
2014-02-08disas: Implement disassembly output for A64Claudio Fontana
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell
2014-01-31target-arm: A64: Add SIMD shift by immediateAlex Bennée
2014-01-31target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell
2014-01-31target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell
2014-01-31target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell
2014-01-31target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell
2014-01-31target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell
2014-01-31target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell
2014-01-31target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell
2014-01-31target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton
2014-01-31target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton
2014-01-31target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZWill Newton
2014-01-31target-arm: Add set_neon_rmode helperWill Newton
2014-01-31target-arm: Add support for AArch32 SIMD VRINTXWill Newton
2014-01-31target-arm: Add support for AArch32 FP VRINTXWill Newton
2014-01-31target-arm: Add support for AArch32 FP VRINTZWill Newton
2014-01-31target-arm: Add support for AArch32 FP VRINTRWill Newton
2014-01-31target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTMWill Newton
2014-01-31target-arm: Move arm_rmode_to_sf to a shared location.Will Newton
2014-01-31ARM: Convert MIDR to a propertyAlistair Francis
2014-01-31target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell
2014-01-31target-arm: A64: Add SIMD modified immediate groupAlex Bennée
2014-01-31target-arm: A64: Add SIMD copy operationsAlex Bennée
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