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AgeCommit message (Expand)Author
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias
2015-09-08target-arm: Log the target EL when taking exceptionsEdgar E. Iglesias
2015-09-08target-arm: Fix default_exception_el() function for the case when EL3 is not ...Sergey Sorokin
2015-09-07target-arm: Refactor CPU affinity handlingPavel Fedin
2015-09-07target-arm: Fix arm_excp_unmasked() functionSergey Sorokin
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite
2015-09-07arm: cpu: assert() on no-EL2 virt IRQ error condition.Peter Crosthwaite
2015-09-07target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell
2015-09-07target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter blockPeter Maydell
2015-09-07target-arm/arm-semi.c: Implement A64 specific SyncCacheRange callPeter Maydell
2015-09-07target-arm/arm-semi.c: Support widening APIs to 64 bitsPeter Maydell
2015-09-07target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]'Peter Maydell
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington
2015-09-07target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdbPeter Maydell
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell
2015-08-25target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell
2015-08-25target-arm: Implement missing AFSR registersPeter Maydell
2015-08-25target-arm: Implement missing AMAIR registersPeter Maydell
2015-08-25target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registersPeter Maydell
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson
2015-08-13target-arm: Add AArch32 banked register access to secure physical timerPeter Maydell
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell
2015-08-13Introduce gic_class_name() instead of repeating conditionPavel Fedin
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias
2015-08-13target-arm: Pass timeridx as argument to various timer functionsEdgar E. Iglesias
2015-08-13target-arm: Rename and move gt_cnt_resetEdgar E. Iglesias
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias
2015-07-21target-arm: kvm: Differentiate registers based on write-back levelsChristoffer Dall
2015-07-15target-arm: Fix broken SCTLR_EL3 resetPeter Maydell
2015-07-09disas: arm: QOMify target specific disas setupPeter Crosthwaite
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite
2015-07-09cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite
2015-07-09cpu: Add Error argument to cpu_exec_init()Bharata B Rao
2015-07-07crypto: move built-in AES implementation into crypto/Daniel P. Berrange
2015-07-06target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov
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