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2010-12-07ARM: Implement VCVT to 16 bit integer using new softfloat routinesPeter Maydell
Use the softfloat conversion routines for conversion to 16 bit integers, because just casting to a 16 bit type truncates the value rather than saturating it at 16-bit MAXINT/MININT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed pointPeter Maydell
VCVT of 16 bit fixed point to float should ignore the top 16 bits of the source register. Cast to int16_t and friends rather than int16 -- the former is guaranteed exactly 16 bits wide where the latter is merely at least 16 bits wide (and so is usually 32 bits). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for single<->double conversion of NaNPeter Maydell
The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for float-to-integer conversion of NaNPeter Maydell
The ARM architecture mandates that converting a NaN value to integer gives zero (if Invalid Operation FP exceptions are not being trapped). This isn't the behaviour of the SoftFloat library, so NaNs must be special-cased. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix sense of to_integer bit in Neon VCVT float/int conversionPeter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of Neon forms of VCVT between float and fixed pointPeter Maydell
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of VFP forms of VCVT between float and int/fixedPeter Maydell
Correct the decoding of source and destination registers for the VFP forms of the VCVT instructions which convert between floating point and integer or fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: fix ldrexd/strexdPeter Maydell
Correct ldrexd and strexd code to always read and write the high word of the 64-bit value from addr+4. Also make ldrexd and strexd agree that for a 64 bit value the address in env->exclusive_addr is that of the low word. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/670883 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Handle 'smc' as an undefined instructionAdam Lackorzynski
Refine check on bkpt so that smc and undefined instruction encodings are handled as an undefined instruction and trap. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Fix mixup in decoding of saturating add and subJohan Bengtsson
The thumb2 decoder contained a mixup between the bit controlling doubling and the bit controlling if the operation was an add or a sub. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Add support for PKHxx in thumb2Johan Bengtsson
The PKHxx instructions were not recognized by the thumb2 decoder. The solution provided in this changeset is identical to the arm-mode implementation. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-03ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C codePeter Maydell
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C code as well as generated code, so we can use them to read and write the FPSCR when saving and restoring VFP registers across signal handlers in linux-user mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-12-03ARM: enable XScale/iWMMXT in linux-user modePeter Maydell
In linux-user mode, the XScale/iWMMXT coprocessors must be enabled at reset so that we can run code that uses these instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2010-12-03[PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()Peter Maydell
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-01target-arm : fix parallel saturated subtraction implementationChih-Min Chao
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-arm : fix thumb2 parallel add/sub opcode decodingChih-Min Chao
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-arm: fix addsub/subadd implementationChih-Min Chao
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11NEON vldN optimizationPaul Brook
When combining multiple values as part of a NEON array load, do explcit shift/or rather than using gen_bfi. This voids redundant mask operations. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-05-31arm: fix arm kernel boot for non zero start addrLars Munch
Booting an arm kernel has been broken a while when booting from non zero start address. This is due to the order of events: board init loads the kernel and sets register 15 to the start address and then qemu_system_reset reset the cpu making register 15 zero again. This patch fixes the usage of the register 15 start address trick in combination with arm_load_kernel. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-28arm: prevent coprocessor IO resetLars Munch
This prevent coprocessor IO structure from being reset on cpu reset. This was a problem for PXA which uses coprocessor 6 and 14. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25arm: remove dead assignments, spotted by clang analyzerBlue Swirl
Value stored is never read. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-08target-arm: fix neon vmon/vmvn with modified immediateJuha Riihimäki
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com> Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08target-arm: resource leak fixes for iwmmxt disassembleLars Munch
This patch fixes few resource leaks in the iwmmxt disassemble. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05Fix arm-linux-userPaul Brook
Only include hw/loader.h from target-arm/helper.c when building for system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05ARMv7-M reset fixesPaul Brook
Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board reset routine to call this. Also load values directly from ROM as images have not been copied yet. Avoid clearing the NVIC pointer on cpu reset. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-27target-arm: disable PAGE_EXEC for XN pagesRabin Vincent
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection checking if the page is already in the TLB. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23target-arm: Fix handling of AL condition in IT instructionJohan Bengtsson
Do not try to insert a conditional jump over next instruction when the condition code is AL as this will trigger an internal error. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-17Large page TLB flushPaul Brook
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-13target-arm: make RFE usable with any registerAdam Lackorzynski
The rfe instruction can be used with any register, not just sp. Adjust the condition check accordingly. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson
Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-06target-arm: Fix missing 'return' in SRS handling.Adam Lackorzynski
There's a return missing in the srs handling which leads to srs always being treated an an invalid op. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon vshll instruction fixJuha Riihimäki
implementation only widened the 32bit source vector elements into a 64bit destination vector but forgot to perform the actual shifting operation. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHNRiku Voipio
The rounding/truncating options were inverted. truncating was done when rounding was meant and vice verse. Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23ARM CP15 tls fixPaul Brook
Fix temporary handling in cp15 tls register load/store. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: support thumb exception handlersRabin Vincent
When handling an exception, switch to the correct mode based on the Thumb Exception (TE) bit in the SCTLR. Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-19target-arm: implement Thumb-2 exception returnRabin Vincent
Support the "subs pc, lr" Thumb-2 exception return instruction. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: fix thumb CPSRabin Vincent
The Thumb CPS currently does not work correctly: CPSID touches more bits than the instruction wants to, and CPSIE does nothing. Fix it by passing the correct mask (the "affect" bits) and value. Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-06target-arm: refactor cp15.c13 register accessRiku Voipio
Access the cp15.c13 TLS registers directly with TCG ops instead of with a slow helper. If the the cp15 read/write was not TLS register access, fall back to the cp15 helper. This makes accessing __thread variables in linux-user when apps are compiled with -mtp=cp15 possible. legal cp15 register to acces from linux-user are already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available only on ARMv6K and newer. Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-01-19kill regs_to_env and env_to_regsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-12-24target-arm: fix strexdAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22ARM atomic ops rewritePaul Brook
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM Cortex-A9 cpu supportPaul Brook
Basic Cortex-A9 support. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM FP16 supportPaul Brook
Implement the ARM VFP half precision floating point extensions. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-10-27target-arm: use native tcg-ops for ror/bic/vornAurelien Jarno
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon shift helper functionsJuha Riihimäki
Current code is broken at least on recent compilers, comparison between signed and unsigned types yield incorrect code and render the neon shift helper functions defunct. This is the third revision of this patch, casting all comparisons with the sizeof operator to signed ssize_t type to force comparisons to be between signed integral types. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-27target-arm: fix neon vsri, vshl and vsli opsJuha Riihimäki
Shift by immediate value is incorrectly overwritten by a temporary variable in the processing of NEON vsri, vshl and vsli instructions. This patch has been revised to also include a fix for the special case where the code would previously try to shift an integer value over 31 bits left/right. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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