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path: root/target-arm/translate.c
AgeCommit message (Expand)Author
2015-02-05target-arm: Use correct mmu_idx for unprivileged loads and storesPeter Maydell
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell
2015-02-05target-arm: check that LSB <= MSB in BFI instructionKirill Batuzov
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2015-01-03translate: check cflags instead of use_icount globalPaolo Bonzini
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov
2014-11-04target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()Peter Maydell
2014-11-04target-arm/translate.c: Don't pass CPUARMState around in the decoderPeter Maydell
2014-11-04target-arm/translate.c: Don't use IS_M()Peter Maydell
2014-11-04target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()Peter Maydell
2014-11-04target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macrosPeter Maydell
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows
2014-10-24target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0Peter Maydell
2014-10-24target-arm: Add support for A32 and T32 HVC and SMC insnsPeter Maydell
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell
2014-06-09target-arm: A32/T32: Mask CRC value in calling code, not helperPeter Maydell
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell
2014-06-09target-arm: Allow 3reg_wide undefreq to encode more bad size optionsPeter Maydell
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel
2014-06-05target-arm: move arm_*_code to a separate filePaolo Bonzini
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson
2014-05-27target-arm: Add SPSR entries for EL2/HYP and EL3/MONEdgar E. Iglesias
2014-05-27target-arm: A32: Use get_mem_index for load/storesEdgar E. Iglesias
2014-05-27target-arm/translate.c: Use get_mem_index() for SRS memory accessesPeter Maydell
2014-05-27target-arm/translate.c: Clean up mmu index handling for ldrt/strtPeter Maydell
2014-04-17arm: translate.c: Fix smlald InstructionPeter Crosthwaite
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell
2014-04-17target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1Peter Maydell
2014-04-17target-arm: Add support for generating exceptions with syndrome informationPeter Maydell
2014-04-17target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell
2014-04-17target-arm: Split out private-to-target functions into internals.hPeter Maydell
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
2014-03-17target-arm: A64: Implement PMULL instructionPeter Maydell
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
2014-03-10target-arm: Implement WFE as a yield operationPeter Maydell
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton
2014-02-20target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell
2014-02-20target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell
2014-02-08target-arm: Add support for AArch32 64bit VCVTB and VCVTTWill Newton
2014-01-31target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTMWill Newton
2014-01-31target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTMWill Newton
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