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path: root/target-arm/translate.c
AgeCommit message (Expand)Author
2016-10-17Fix masking of PC lower bits when doing exception returnsPeter Maydell
2016-10-04target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6Peter Maydell
2016-09-16target-arm: Generate fences in ARMv7 frontendPranith Kumar
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova
2016-06-14target-arm: Don't permit ARMv8-only Neon insns on ARMv7Peter Maydell
2016-06-06target-arm: A64: Create Instruction Syndromes for Data AbortsEdgar E. Iglesias
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov
2016-05-12tcg: Clean up direct block chaining safety checksSergey Fedorov
2016-03-22target-arm: dfilter support for in_asmAlex Bennée
2016-03-16target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell
2016-03-04target-arm: Only trap SRS from S-EL1 if specified mode is MONRalf-Philipp Weinmann
2016-03-04target-arm: implement BE32 mode in system emulationPaolo Bonzini
2016-03-04target-arm: implement setendPaolo Bonzini
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini
2016-03-04target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova
2016-02-26target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell
2016-02-18target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell
2016-02-18target-arm: Clean up trap/undef handling of SRSPeter Maydell
2016-02-11target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell
2016-02-11target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
2016-02-09tcg: Remove lingering references to gen_opc_bufRichard Henderson
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
2016-01-18target-arm: Clean up includesPeter Maydell
2015-12-17target-arm: Fix and improve AA32 singlestep translation completion codeSergey Fedorov
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann
2015-11-19target-arm: Update condexec before arch BP check in AA32 translationSergey Fedorov
2015-11-19target-arm: Update condexec before CP access check in AA32 translationSergey Fedorov
2015-11-12target-arm: Update PC before calling gen_helper_check_breakpoints()Sergey Fedorov
2015-11-10target-arm: Clean up DISAS_UPDATE usage in AArch32 translation codeSergey Fedorov
2015-11-03target-arm: Report S/NS status in the CPU debug logsPeter Maydell
2015-10-28target-*: Advance pc after recognizing a breakpointRichard Henderson
2015-10-27target-arm/translate.c: Handle non-executable page-straddling Thumb insnsPeter Maydell
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-arm: Add condexec state to insn_startRichard Henderson
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-09-14target-arm: Handle always condition codes within arm_test_ccRichard Henderson
2015-09-14target-arm: Introduce DisasCompareRichard Henderson
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