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2013-03-05target-arm: Don't decode RFE or SRS on M profile coresPeter Maydell
M profile cores do not have the RFE or SRS instructions, so correctly UNDEF these insn patterns on those cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-05target-arm: Factor out handling of SRS instructionPeter Maydell
Factor out the handling of the SRS instruction rather than duplicating it between the Thumb and ARM decoders. This in passing fixes two bugs in the Thumb decoder's SRS handling which didn't exist in the ARM decoder: * (LP:1079080) storing CPSR rather than SPSR (fixed in the ARM decoder in commit c67b6b71 in 2009) * failing to free the 'addr' TCG temp in the writeback case Reported-by: Cesson Vincent <vcesson@stmi.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell
The gen_icount_start/end functions are now somewhat misnamed since they are useful for generic "start/end of TB" code, used for more than just icount. Rename them to gen_tb_start/end. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-25target-arm: Fix sbc_CC carryRichard Henderson
While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits, it does not produce the correct carry-out to bit 33. Do exactly what the manual says. Using the ~T1 makes the add and subtract code paths nearly identical, so have sbc_CC use adc_CC. Cc: Peter Maydell <peter.maydell@linaro.org> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-25arm/translate.c: Fix adc_CC/sbc_CC implementationPeter Crosthwaite
commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and 2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CC and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path) are incorrect. The new logic is: CF:NF = 0:A +/- 0:CF CF:NF = CF:A +/- 0:B The lower 32 bits of the intermediate result stored in NF needs to be passes into the second addition in place of A (s/CF:A/CF:NF): CF:NF = 0:A +/- 0:CF CF:NF = CF:NF +/- 0:B This patch fixes the issue. Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-02-23target-arm: Implement sbc_cc inlineRichard Henderson
Use sub2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Implement adc_cc inlineRichard Henderson
Use add2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use add2 in gen_add_CCRichard Henderson
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-23target-arm: Use mul[us]2 in gen_mul[us]_i64_i32Richard Henderson
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-01-30target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writesPeter Maydell
Fix a leak of a TCG temporary in code paths for VFP system register writes for cases which UNDEF or are write-ignored. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-12-19misc: move include files to include/qemu/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19exec: move include files to include/exec/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-17TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-17TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-10disas: avoid using cpu_single_envBlue Swirl
Pass around CPUArchState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Richard Henderson <rth@twiddle.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
2012-10-24target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell
Implement abs_i32 inline (with movcond) rather than using a helper function. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-24target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell
Use the TCG operation to do Neon 64 bit negations rather than calling a helper routine for it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-17target-arm/translate: Fix RRX operandsPeter Crosthwaite
Instructions that both use the RRX second operand and update CS were incorrect, as the Carry flag was updated too early. An example of such an instruction would be: ands r12,r13,RRX Ands, because of the "s" flag will update the carry flag. But the RRX second operand rotates through the C flag which should happen before the update. Fixed the ordering of the two, the old carry is read by "r13,RRX" before being updated. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reported-by: Vinesh Peringat <vineshp@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-05target-arm: use deposit instead of hardcoded versionAurelien Jarno
Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno
Now that the movcond TCG op is available, it's possible to replace shl and shr helpers by TCG code. The code generated by TCG is slightly longer than the code generated by GCC for the helper but is still worth it as this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno
Now that the setcond TCG op is available, it's possible to replace add_cc and sub_cc helpers by TCG code. The code generated by TCG is actually very close to the one generated by GCC for the helper, and this avoid all the consequences of using an helper: globals saved back to memory, no possible optimization, call overhead, etc. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: use globals for CC flagsAurelien Jarno
Use globals for CC flags instead of loading/storing them each they are accessed. This allows some optimizations to be performed by the TCG optimization passes. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-05target-arm: Reinstate display of VFP registers in cpu_dump_statePeter Maydell
Reinstate the display of VFP registers in cpu_dump_state(), if the CPU has them (this code had been #if 0'd out a for a long time). We drop the attempt ot display the values as floating point, since this makes assumptions about the host 'float' and 'double' formats and is not done by eg the i386 cpu_dump_state(). This display is gated on the CPU_DUMP_FPU flag, as for x86. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-27Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson
For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15target-arm: final conversion to AREG0 free modeBlue Swirl
Convert code load functions and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15target-arm: convert remaining helpersBlue Swirl
Convert remaining helpers to AREG0 free mode: add an explicit CPUState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-09-15target-arm: convert void helpersBlue Swirl
Add an explicit CPUState parameter instead of relying on AREG0. For easier review, convert only op helpers which don't return any value. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-08-10target-arm: Fix typos in commentsPeter Maydell
Fix a variety of typos in comments in target-arm files. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-08-10arm: translate: comment typo - s/middel/middle/Peter A. G. Crosthwaite
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2012-07-12target-arm: Fix TCG temp handling in 64 bit cp writesPeter Maydell
Fix errors in the TCG temp handling in the 64 bit coprocessor write path: we were reusing a 32 bit temp after it had been freed by store_reg(), and failing to free a 64 bit temp. This bug has no visible effect at this point because there aren't any non-NOP 64 bit registers yet; it needs to be fixed as a prerequisite for the 64 bit registers in LPAE support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-07-12target-arm: Fix CP15 based WFIPaul Brook
The coprocessor register rework broke cp15 based WFI instructions. We incorrectly fall through the normal register write case, which incorrectly adds a forced block termination. We've already done a special version of this (DISAS_WFI), so return immediately. Signed-off-by: Paul Brook <paul@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell
There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Move block cache ops to new cp15 frameworkPeter Maydell
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert performance monitor registersPeter Maydell
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TLS registersPeter Maydell
Convert TLS registers to the new cp15 framework Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert WFI/barriers special cases to cp_reginfoPeter Maydell
Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert TEECR, TEEHBR to new schemePeter Maydell
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Convert debug registers to cp_reginfoPeter Maydell
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: Remove old cpu_arm_set_cp_io infrastructurePeter Maydell
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-27target-arm: Make SETEND respect bswap_code (BE8) settingPeter Maydell
Make the SETEND instruction respect the setting of bswap_code, so that in BE8 mode we UNDEF for attempts to switch into little-endian mode and nop for attempts to stay in big-endian mode. (This is the inverse of the existing handling of SETEND in the more common little-endian setup, which we use since we don't implement the architecturally-mandated dynamic endianness switching.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-06Userspace ARM BE8 supportPaul Brook
Add support for ARM BE8 userspace binaries. i.e. big-endian data and little-endian code. In principle LE8 mode is also possible, but AFAIK has never actually been implemented/used. System emulation doesn't have any useable big-endian board models, but should in principle work once you fix that. Dynamic endianness switching requires messing with data accesses, preferably with TCG cooperation, and is orthogonal to BE8 support. Signed-off-by: Paul Brook <paul@codesourcery.com> [PMM: various changes, mostly as per my suggestions in code review: * rebase * use EF_ defines rather than hardcoded constants * make bswap_code a bool for future VMSTATE macro compatibility * update comment in cpu.h about TB flags bit field usage * factor out load-code-and-swap into arm_ld*_code functions and get_user_code* macros * fix stray trailing space at end of line * added braces in disas.c to satisfy checkpatch ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-03-30ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.Andrew Towers
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu does not support ARM1156 at this time.) MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores. Reference: ARM DDI 0211H, 0290G, 0301H, 0360E. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html Without this change, the linux kernel will not boot with VFP support enabled under ARM1176 system emulation, due to the unconditional use of MVFR1 at the end of vfp_init() in arch/arm/vfp/vfpmodule.c: VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5 Internal error: Oops - undefined instruction: 0 [#1] Signed-off-by: Andrew Towers <atowers@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-15target-arm: Decode SETEND correctly in ThumbPeter Maydell
Decode the SETEND instruction correctly in Thumb mode, rather than accidentally treating it like CPS. We don't support BE8 mode, but this change brings the Thumb mode in to line with behaviour in ARM mode: 'SETEND BE' is not supported and will provoke an UNDEF exception, but 'SETEND LE' is correctly handled as a no-op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reported-by: Daniel Forsgren <daniel.forsgren@enea.com> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2012-03-14target-arm: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
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