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QEMU is a generic and open source machine & userspace emulator and virtualizer
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target-arm
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translate-a64.c
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Author
2014-01-31
target-arm: A64: Add SIMD shift by immediate
Alex Bennée
2014-01-31
target-arm: A64: Add simple SIMD 3-same floating point ops
Peter Maydell
2014-01-31
target-arm: A64: Add integer ops from SIMD 3-same group
Peter Maydell
2014-01-31
target-arm: A64: Add logic ops from SIMD 3 same group
Peter Maydell
2014-01-31
target-arm: A64: Add top level decode for SIMD 3-same group
Peter Maydell
2014-01-31
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Peter Maydell
2014-01-31
target-arm: A64: Add SIMD three-different ABDL instructions
Peter Maydell
2014-01-31
target-arm: A64: Add SIMD three-different multiply accumulate insns
Peter Maydell
2014-01-31
target-arm: Move arm_rmode_to_sf to a shared location.
Will Newton
2014-01-31
target-arm: A64: Add SIMD scalar copy instructions
Peter Maydell
2014-01-31
target-arm: A64: Add SIMD modified immediate group
Alex Bennée
2014-01-31
target-arm: A64: Add SIMD copy operations
Alex Bennée
2014-01-31
target-arm: A64: Add SIMD across-lanes instructions
Michael Matz
2014-01-31
target-arm: A64: Add SIMD ZIP/UZP/TRN
Michael Matz
2014-01-31
target-arm: A64: Add SIMD TBL/TBLX
Michael Matz
2014-01-31
target-arm: A64: Add SIMD EXT
Peter Maydell
2014-01-31
target-arm: A64: Add decode skeleton for SIMD data processing insns
Alex Bennée
2014-01-31
target-arm: A64: Add SIMD ld/st single
Peter Maydell
2014-01-31
target-arm: A64: Add SIMD ld/st multiple
Alex Bennée
2014-01-08
target-arm: A64: Add support for FCVT between half, single and double
Peter Maydell
2014-01-08
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
Peter Maydell
2014-01-08
target-arm: A64: Add floating-point<->integer conversion instructions
Will Newton
2014-01-08
target-arm: A64: Add floating-point<->fixed-point instructions
Alexander Graf
2014-01-08
target-arm: A64: Add support for floating point cond select
Claudio Fontana
2014-01-08
target-arm: A64: Add support for floating point conditional compare
Claudio Fontana
2014-01-08
target-arm: A64: Add support for floating point compare
Claudio Fontana
2014-01-08
target-arm: A64: Add fmov (scalar, immediate) instruction
Alexander Graf
2014-01-08
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
Alexander Graf
2014-01-08
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
Alexander Graf
2014-01-08
target-arm: A64: Fix vector register access on bigendian hosts
Peter Maydell
2014-01-08
target-arm: A64: Add support for dumping AArch64 VFP register state
Alexander Graf
2014-01-08
target-arm: A64: support for ld/st/cl exclusive
Michael Matz
2014-01-08
target-arm: aarch64: add support for ld lit
Alexander Graf
2014-01-08
target-arm: A64: add support for conditional compare insns
Claudio Fontana
2014-01-08
target-arm: A64: add support for add/sub with carry
Claudio Fontana
2014-01-07
target-arm: A64: Implement minimal set of EL0-visible sysregs
Peter Maydell
2014-01-07
target-arm: A64: Implement MRS/MSR/SYS/SYSL
Peter Maydell
2014-01-07
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
Peter Maydell
2013-12-23
target-arm: A64: implement FMOV
Peter Maydell
2013-12-23
target-arm: A64: Add decoder skeleton for FP instructions
Peter Maydell
2013-12-23
target-arm: A64: implement SVC, BRK
Alexander Graf
2013-12-23
target-arm: A64: add support for 3 src data proc insns
Alexander Graf
2013-12-23
target-arm: A64: add support for move wide instructions
Alex Bennée
2013-12-23
target-arm: A64: add support for add, addi, sub, subi
Alex Bennée
2013-12-23
target-arm: A64: add support for ld/st with index
Alex Bennée
2013-12-23
target-arm: A64: add support for ld/st with reg offset
Alex Bennée
2013-12-23
target-arm: A64: add support for ld/st unsigned imm
Alex Bennée
2013-12-23
target-arm: A64: add support for ld/st pair
Peter Maydell
2013-12-17
target-arm: A64: add support for logical (immediate) insns
Alexander Graf
2013-12-17
target-arm: A64: add support for 1-src CLS insn
Claudio Fontana
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