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QEMU is a generic and open source machine & userspace emulator and virtualizer
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target-arm
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translate-a64.c
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2014-04-17
target-arm: A64: fix unallocated test of scalar SQXTUN
Alex Bennée
2014-04-17
target-arm: Implement AArch64 EL1 exception handling
Rob Herring
2014-04-17
target-arm: A64: Implement DC ZVA
Peter Maydell
2014-04-17
target-arm: A64: Add assertion that FP access was checked
Peter Maydell
2014-04-17
target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
Peter Maydell
2014-04-17
target-arm: Add support for generating exceptions with syndrome information
Peter Maydell
2014-04-17
target-arm: Provide correct syndrome information for cpreg access traps
Peter Maydell
2014-04-17
target-arm: Split out private-to-target functions into internals.h
Peter Maydell
2014-03-24
target-arm: Fix A64 Neon MLS
Peter Maydell
2014-03-18
target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
Alex Bennée
2014-03-18
target-arm: A64: Add saturating int ops (SQNEG/SQABS)
Alex Bennée
2014-03-17
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
Alex Bennée
2014-03-17
target-arm: A64: Implement FCVTXN
Peter Maydell
2014-03-17
target-arm: A64: Implement scalar saturating narrow ops
Alex Bennée
2014-03-17
target-arm: A64: Move handle_2misc_narrow function
Alex Bennée
2014-03-17
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
Alex Bennée
2014-03-17
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
Peter Maydell
2014-03-17
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
Peter Maydell
2014-03-17
target-arm: A64: Implement FRINT*
Peter Maydell
2014-03-17
target-arm: A64: Implement SRI
Peter Maydell
2014-03-17
target-arm: A64: Add FRECPX (reciprocal exponent)
Alex Bennée
2014-03-17
target-arm: A64: List unsupported shift-imm opcodes
Peter Maydell
2014-03-17
target-arm: A64: Implement FCVTL
Peter Maydell
2014-03-17
target-arm: A64: Implement FCVTN
Peter Maydell
2014-03-17
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
Peter Maydell
2014-03-17
target-arm: A64: Implement SHLL, SHLL2
Peter Maydell
2014-03-17
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
Peter Maydell
2014-03-17
target-arm: A64: Saturating and narrowing shift ops
Alex Bennée
2014-03-17
target-arm: A64: Add remaining CLS/Z vector ops
Alex Bennée
2014-03-17
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
Alex Bennée
2014-03-17
target-arm: A64: Add last AdvSIMD Integer to FP ops
Alex Bennée
2014-03-17
target-arm: A64: Fix bug in add_sub_ext handling of rn
Alex Bennée
2014-03-17
target-arm: A64: Implement PMULL instruction
Peter Maydell
2014-03-13
cpu: Move breakpoints field from CPU_COMMON to CPUState
Andreas Färber
2014-03-10
target-arm: Fix intptr_t vs tcg_target_long
Richard Henderson
2014-02-26
target-arm: A64: Implement MSR (immediate) instructions
Peter Maydell
2014-02-26
target-arm: A64: Implement WFI
Peter Maydell
2014-02-26
target-arm: Get MMU index information correct for A64 code
Peter Maydell
2014-02-26
target-arm: Implement AArch64 CurrentEL sysreg
Peter Maydell
2014-02-20
target-arm: A64: Implement unprivileged load/store
Peter Maydell
2014-02-20
target-arm: A64: Implement narrowing three-reg-diff operations
Peter Maydell
2014-02-20
target-arm: A64: Implement the wide 3-reg-different operations
Peter Maydell
2014-02-20
target-arm: A64: Add most remaining three-reg-diff widening ops
Peter Maydell
2014-02-20
target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
Peter Maydell
2014-02-20
target-arm: A64: Implement store-exclusive for system mode
Peter Maydell
2014-02-20
target-arm: Remove unnecessary code now read/write fns can't fail
Peter Maydell
2014-02-20
target-arm: Split cpreg access checks out from read/write functions
Peter Maydell
2014-02-20
target-arm: Log bad system register accesses with LOG_UNIMP
Peter Maydell
2014-02-20
target-arm: A64: Implement remaining 3-same instructions
Peter Maydell
2014-02-20
target-arm: A64: Implement floating point pairwise insns
Alex Bennée
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