Age | Commit message (Expand) | Author |
2015-11-24 | target-arm/translate-a64.c: Correct unallocated checks for ldst_excl | Peter Maydell |
2015-11-12 | target-arm: Update PC before calling gen_helper_check_breakpoints() | Sergey Fedorov |
2015-11-03 | target-arm: Report S/NS status in the CPU debug logs | Peter Maydell |
2015-11-03 | target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 | Peter Maydell |
2015-10-28 | target-*: Advance pc after recognizing a breakpoint | Richard Henderson |
2015-10-16 | target-arm: Fix CPU breakpoint handling | Sergey Fedorov |
2015-10-16 | target-arm: Break the TB after ISB to execute self-modified code correctly | Sergey Sorokin |
2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson |
2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson |
2015-10-07 | target-arm: Add condexec state to insn_start | Richard Henderson |
2015-10-07 | target-*: Introduce and use cpu_breakpoint_test | Richard Henderson |
2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson |
2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson |
2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson |
2015-09-14 | target-arm: Use tcg_gen_extrh_i64_i32 | Richard Henderson |
2015-09-14 | target-arm: Recognize ROR | Richard Henderson |
2015-09-14 | target-arm: Eliminate unnecessary zero-extend in disas_bitfield | Richard Henderson |
2015-09-14 | target-arm: Recognize UXTB, UXTH, LSR, LSL | Richard Henderson |
2015-09-14 | target-arm: Recognize SXTB, SXTH, SXTW, ASR | Richard Henderson |
2015-09-14 | target-arm: Implement fcsel with movcond | Richard Henderson |
2015-09-14 | target-arm: Implement ccmp branchless | Richard Henderson |
2015-09-14 | target-arm: Use setcond and movcond for csel | Richard Henderson |
2015-09-14 | target-arm: Share all common TCG temporaries | Richard Henderson |
2015-09-08 | target-arm: Fix default_exception_el() function for the case when EL3 is not ... | Sergey Sorokin |
2015-09-07 | target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction | Peter Maydell |
2015-08-24 | tcg: Remove tcg_gen_trunc_i64_i32 | Richard Henderson |
2015-07-06 | target-arm: Split DISAS_YIELD from DISAS_WFE | Peter Maydell |
2015-06-22 | disas: Remove uses of CPU env | Peter Crosthwaite |
2015-05-29 | target-arm: Don't halt on WFI unless we don't have any work | Peter Maydell |
2015-05-29 | target-arm: Extend FP checks to use an EL | Greg Bellows |
2015-05-29 | target-arm: Make singlestate TB flags common between AArch32/64 | Peter Maydell |
2015-05-29 | target-arm: Add exception target el infrastructure | Greg Bellows |
2015-03-13 | tcg: Change translator-side labels to a pointer | Richard Henderson |
2015-02-13 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150212' into staging | Peter Maydell |
2015-02-13 | target-arm: A64: Avoid signed shifts in disas_ldst_pair() | Peter Maydell |
2015-02-13 | target-arm: A64: Avoid left shifting negative integers in disas_pc_rel_addr | Peter Maydell |
2015-02-13 | target-arm: A64: Fix handling of rotate in logic_imm_decode_wmask | Peter Maydell |
2015-02-13 | target-arm: A64: Fix shifts into sign bit | Peter Maydell |
2015-02-12 | tcg: Introduce tcg_op_buf_count and tcg_op_buf_full | Richard Henderson |
2015-02-12 | tcg: Move emit of INDEX_op_end into gen_tb_end | Richard Henderson |
2015-02-05 | target-arm: Use correct mmu_idx for unprivileged loads and stores | Peter Maydell |
2015-02-05 | target-arm: Define correct mmu_idx values and pass them in TB flags | Peter Maydell |
2015-02-05 | target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT | Peter Maydell |
2015-01-03 | gen-icount: check cflags instead of use_icount global | Paolo Bonzini |
2015-01-03 | translate: check cflags instead of use_icount global | Paolo Bonzini |
2014-11-02 | target-arm: A64: remove redundant store | Alex Bennée |
2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows |
2014-10-24 | target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers | Peter Maydell |
2014-09-29 | target-arm: A64: Emulate the SMC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the HVC insn | Edgar E. Iglesias |