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path: root/target-arm/translate-a64.c
AgeCommit message (Expand)Author
2014-03-24target-arm: Fix A64 Neon MLSPeter Maydell
2014-03-18target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée
2014-03-18target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée
2014-03-17target-arm: A64: Implement FCVTXNPeter Maydell
2014-03-17target-arm: A64: Implement scalar saturating narrow opsAlex Bennée
2014-03-17target-arm: A64: Move handle_2misc_narrow functionAlex Bennée
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée
2014-03-17target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categoriesPeter Maydell
2014-03-17target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHLPeter Maydell
2014-03-17target-arm: A64: Implement FRINT*Peter Maydell
2014-03-17target-arm: A64: Implement SRIPeter Maydell
2014-03-17target-arm: A64: Add FRECPX (reciprocal exponent)Alex Bennée
2014-03-17target-arm: A64: List unsupported shift-imm opcodesPeter Maydell
2014-03-17target-arm: A64: Implement FCVTLPeter Maydell
2014-03-17target-arm: A64: Implement FCVTNPeter Maydell
2014-03-17target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructionsPeter Maydell
2014-03-17target-arm: A64: Implement SHLL, SHLL2Peter Maydell
2014-03-17target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALPPeter Maydell
2014-03-17target-arm: A64: Saturating and narrowing shift opsAlex Bennée
2014-03-17target-arm: A64: Add remaining CLS/Z vector opsAlex Bennée
2014-03-17target-arm: A64: Add FSQRT to C3.6.17 (two misc)Alex Bennée
2014-03-17target-arm: A64: Add last AdvSIMD Integer to FP opsAlex Bennée
2014-03-17target-arm: A64: Fix bug in add_sub_ext handling of rnAlex Bennée
2014-03-17target-arm: A64: Implement PMULL instructionPeter Maydell
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
2014-03-10target-arm: Fix intptr_t vs tcg_target_longRichard Henderson
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell
2014-02-26target-arm: A64: Implement WFIPeter Maydell
2014-02-26target-arm: Get MMU index information correct for A64 codePeter Maydell
2014-02-26target-arm: Implement AArch64 CurrentEL sysregPeter Maydell
2014-02-20target-arm: A64: Implement unprivileged load/storePeter Maydell
2014-02-20target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell
2014-02-20target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell
2014-02-20target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell
2014-02-20target-arm: A64: Add opcode comments to disas_simd_three_reg_diffPeter Maydell
2014-02-20target-arm: A64: Implement store-exclusive for system modePeter Maydell
2014-02-20target-arm: Remove unnecessary code now read/write fns can't failPeter Maydell
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell
2014-02-20target-arm: Log bad system register accesses with LOG_UNIMPPeter Maydell
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell
2014-02-20target-arm: A64: Implement floating point pairwise insnsAlex Bennée
2014-02-20target-arm: A64: Implement SIMD FP compare and set insnsAlex Bennée
2014-02-20target-arm: A64: Implement scalar three different instructionsPeter Maydell
2014-02-20target-arm: A64: Implement SIMD scalar indexed instructionsPeter Maydell
2014-02-20target-arm: A64: Implement long vector x indexed insnsPeter Maydell
2014-02-20target-arm: A64: Implement plain vector SIMD indexed element insnsPeter Maydell
2014-02-08disas: Implement disassembly output for A64Claudio Fontana
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée
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