aboutsummaryrefslogtreecommitdiff
path: root/target-arm/translate-a64.c
AgeCommit message (Expand)Author
2014-02-08disas: Implement disassembly output for A64Claudio Fontana
2014-02-08target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc groupPeter Maydell
2014-02-08target-arm: A64: Add 2-reg-misc REV* instructionsAlex Bennée
2014-02-08target-arm: A64: Add narrowing 2-reg-misc instructionsPeter Maydell
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell
2014-02-08target-arm: A64: Implement 2-register misc compares, ABS, NEGPeter Maydell
2014-02-08target-arm: A64: Add skeleton decode for SIMD 2-reg misc groupPeter Maydell
2014-02-08target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg miscPeter Maydell
2014-02-08target-arm: A64: Implement remaining integer scalar-3-same insnsPeter Maydell
2014-02-08target-arm: A64: Implement scalar pairwise opsPeter Maydell
2014-02-08target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMDPeter Maydell
2014-02-08target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insnsPeter Maydell
2014-02-08target-arm: A64: Implement SIMD 3-reg-same shift and saturate insnsPeter Maydell
2014-01-31target-arm: A64: Add SIMD shift by immediateAlex Bennée
2014-01-31target-arm: A64: Add simple SIMD 3-same floating point opsPeter Maydell
2014-01-31target-arm: A64: Add integer ops from SIMD 3-same groupPeter Maydell
2014-01-31target-arm: A64: Add logic ops from SIMD 3 same groupPeter Maydell
2014-01-31target-arm: A64: Add top level decode for SIMD 3-same groupPeter Maydell
2014-01-31target-arm: A64: Add SIMD scalar 3 same add, sub and compare opsPeter Maydell
2014-01-31target-arm: A64: Add SIMD three-different ABDL instructionsPeter Maydell
2014-01-31target-arm: A64: Add SIMD three-different multiply accumulate insnsPeter Maydell
2014-01-31target-arm: Move arm_rmode_to_sf to a shared location.Will Newton
2014-01-31target-arm: A64: Add SIMD scalar copy instructionsPeter Maydell
2014-01-31target-arm: A64: Add SIMD modified immediate groupAlex Bennée
2014-01-31target-arm: A64: Add SIMD copy operationsAlex Bennée
2014-01-31target-arm: A64: Add SIMD across-lanes instructionsMichael Matz
2014-01-31target-arm: A64: Add SIMD ZIP/UZP/TRNMichael Matz
2014-01-31target-arm: A64: Add SIMD TBL/TBLXMichael Matz
2014-01-31target-arm: A64: Add SIMD EXTPeter Maydell
2014-01-31target-arm: A64: Add decode skeleton for SIMD data processing insnsAlex Bennée
2014-01-31target-arm: A64: Add SIMD ld/st singlePeter Maydell
2014-01-31target-arm: A64: Add SIMD ld/st multipleAlex Bennée
2014-01-08target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell
2014-01-08target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell
2014-01-08target-arm: A64: Add floating-point<->integer conversion instructionsWill Newton
2014-01-08target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf
2014-01-08target-arm: A64: Add support for floating point cond selectClaudio Fontana
2014-01-08target-arm: A64: Add support for floating point conditional compareClaudio Fontana
2014-01-08target-arm: A64: Add support for floating point compareClaudio Fontana
2014-01-08target-arm: A64: Add fmov (scalar, immediate) instructionAlexander Graf
2014-01-08target-arm: A64: Add "Floating-point data-processing (3 source)" insnsAlexander Graf
2014-01-08target-arm: A64: Add "Floating-point data-processing (2 source)" insnsAlexander Graf
2014-01-08target-arm: A64: Fix vector register access on bigendian hostsPeter Maydell
2014-01-08target-arm: A64: Add support for dumping AArch64 VFP register stateAlexander Graf
2014-01-08target-arm: A64: support for ld/st/cl exclusiveMichael Matz
2014-01-08target-arm: aarch64: add support for ld litAlexander Graf
2014-01-08target-arm: A64: add support for conditional compare insnsClaudio Fontana
2014-01-08target-arm: A64: add support for add/sub with carryClaudio Fontana
2014-01-07target-arm: A64: Implement minimal set of EL0-visible sysregsPeter Maydell
2014-01-07target-arm: A64: Implement MRS/MSR/SYS/SYSLPeter Maydell
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-05 14:08:33 +0000