Age | Commit message (Expand) | Author |
2014-01-08 | target-arm: A64: Add support for FCVT between half, single and double | Peter Maydell |
2014-01-08 | target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions | Peter Maydell |
2014-01-08 | target-arm: A64: Add floating-point<->integer conversion instructions | Will Newton |
2014-01-08 | target-arm: A64: Add floating-point<->fixed-point instructions | Alexander Graf |
2014-01-08 | target-arm: A64: Add support for floating point cond select | Claudio Fontana |
2014-01-08 | target-arm: A64: Add support for floating point conditional compare | Claudio Fontana |
2014-01-08 | target-arm: A64: Add support for floating point compare | Claudio Fontana |
2014-01-08 | target-arm: A64: Add fmov (scalar, immediate) instruction | Alexander Graf |
2014-01-08 | target-arm: A64: Add "Floating-point data-processing (3 source)" insns | Alexander Graf |
2014-01-08 | target-arm: A64: Add "Floating-point data-processing (2 source)" insns | Alexander Graf |
2014-01-08 | target-arm: A64: Fix vector register access on bigendian hosts | Peter Maydell |
2014-01-08 | target-arm: A64: Add support for dumping AArch64 VFP register state | Alexander Graf |
2014-01-08 | target-arm: A64: support for ld/st/cl exclusive | Michael Matz |
2014-01-08 | target-arm: aarch64: add support for ld lit | Alexander Graf |
2014-01-08 | target-arm: A64: add support for conditional compare insns | Claudio Fontana |
2014-01-08 | target-arm: A64: add support for add/sub with carry | Claudio Fontana |
2014-01-07 | target-arm: A64: Implement minimal set of EL0-visible sysregs | Peter Maydell |
2014-01-07 | target-arm: A64: Implement MRS/MSR/SYS/SYSL | Peter Maydell |
2014-01-07 | target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder | Peter Maydell |
2013-12-23 | target-arm: A64: implement FMOV | Peter Maydell |
2013-12-23 | target-arm: A64: Add decoder skeleton for FP instructions | Peter Maydell |
2013-12-23 | target-arm: A64: implement SVC, BRK | Alexander Graf |
2013-12-23 | target-arm: A64: add support for 3 src data proc insns | Alexander Graf |
2013-12-23 | target-arm: A64: add support for move wide instructions | Alex Bennée |
2013-12-23 | target-arm: A64: add support for add, addi, sub, subi | Alex Bennée |
2013-12-23 | target-arm: A64: add support for ld/st with index | Alex Bennée |
2013-12-23 | target-arm: A64: add support for ld/st with reg offset | Alex Bennée |
2013-12-23 | target-arm: A64: add support for ld/st unsigned imm | Alex Bennée |
2013-12-23 | target-arm: A64: add support for ld/st pair | Peter Maydell |
2013-12-17 | target-arm: A64: add support for logical (immediate) insns | Alexander Graf |
2013-12-17 | target-arm: A64: add support for 1-src CLS insn | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for bitfield insns | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 1-src REV insns | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 1-src RBIT insn | Alexander Graf |
2013-12-17 | target-arm: A64: add support for 1-src data processing and CLZ | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 2-src shift reg insns | Alexander Graf |
2013-12-17 | target-arm: A64: add support for 2-src data processing and DIV | Alexander Graf |
2013-12-17 | target-arm: A64: add support for EXTR | Alexander Graf |
2013-12-17 | target-arm: A64: add support for ADR and ADRP | Alexander Graf |
2013-12-17 | target-arm: A64: add support for logical (shifted register) | Alexander Graf |
2013-12-17 | target-arm: A64: add support for conditional select | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for compare and branch imm | Alexander Graf |
2013-12-17 | target-arm: A64: add support for 'test and branch' imm | Alexander Graf |
2013-12-17 | target-arm: A64: add support for conditional branches | Alexander Graf |
2013-12-17 | target-arm: A64: add support for BR, BLR and RET insns | Alexander Graf |
2013-12-17 | target-arm: A64: add support for B and BL insns | Alexander Graf |
2013-12-17 | target-arm: A64: expand decoding skeleton for system instructions | Claudio Fontana |
2013-12-17 | target-arm: A64: provide skeleton for a64 insn decoding | Claudio Fontana |
2013-12-17 | target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() | Peter Maydell |
2013-12-17 | target-arm: Clean up handling of AArch64 PSTATE | Peter Maydell |