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2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-10-17Fix masking of PC lower bits when doing exception returnsPeter Maydell
In commit 9b6a3ea7a699594 store_reg() was changed to mask both bits 0 and 1 of the new PC value when in ARM mode. Unfortunately this broke the exception return code paths when doing a return from ARM mode to Thumb mode: in some of these we write a new CPSR including new Thumb mode bit via gen_helper_cpsr_write_eret(), and then use store_reg() to write the new PC. In this case if the new CPSR specified Thumb mode then masking bit 1 of the PC is incorrect (these code paths correspond to the v8 ARM ARM pseudocode function AArch32.ExceptionReturn(), which always aligns the new PC appropriately for the new instruction set state). Instead of using store_reg() in exception-return code paths, call a new store_pc_exc_ret() which stores the raw new PC value to env->regs[15], and then mask it appropriately in the subsequent helper_cpsr_write_eret() where the new env->thumb state is available. This fixes a bug introduced by 9b6a3ea7a699594 which caused crashes/hangs or otherwise bad behaviour for Linux when userspace was using Thumb. Reported-by: Jerome Forissier <jerome.forissier@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1476113163-24578-1-git-send-email-peter.maydell@linaro.org
2016-09-06target-arm: Fix lpae bit in FSR on an alignment faultSergey Sorokin
If an alignment fault occurred and target EL is using AArch32, then DFSR/IFSR bit LPAE[9] must be set correctly. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1471283293-169850-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-12Fix confusing argument names in some common functionsSergey Sorokin
There are functions tlb_fill(), cpu_unaligned_access() and do_unaligned_access() that are called with access type and mmu index arguments. But these arguments are named 'is_write' and 'is_user' in their declarations. The patches fix the arguments to avoid a confusion. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1465907177-1399402-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-06-17target-arm: Provide hook to tell GICv3 about changes of security statePeter Maydell
The GICv3 CPU interface needs to know when the CPU it is attached to makes an exception level or mode transition that changes the security state, because whether it is asserting IRQ or FIQ can change depending on these things. Provide a mechanism for letting the GICv3 device register a hook to be called on such changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-5-git-send-email-peter.maydell@linaro.org
2016-06-06target-arm: A64: Create Instruction Syndromes for Data AbortsEdgar E. Iglesias
Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch64. These syndromes are used by hypervisors for example to trap and emulate memory accesses. We save the decoded data out-of-band with the TBs at translation time. When exceptions hit, the extra data attached to the TB is used to recreate the state needed to encode instruction syndromes. This avoids the need to emit moves with every load/store. Based on a suggestion from Peter Maydell. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1462464601-10888-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-12target-arm: Split data abort syndrome generatorPeter Maydell
Split the data abort syndrome generator into two versions: One with a valid Instruction Specific Syndrome (ISS) and another without. The following new flags are supported by the syndrome generator with ISS: * isv - Instruction syndrome valid * sas - Syndrome access size * sse - Syndrome sign extend * srt - Syndrome register transfer * sf - Sixty-Four bit register width * ar - Acquire/Release These flags are not yet used, so this patch has no functional change except that we will now correctly set the IL bit in data abort syndromes without ISS information. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1461931684-1867-5-git-send-email-edgar.iglesias@gmail.com> [PMM: squashed in with patch which was just adding the IL bit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16target-arm: Implement MRS (banked) and MSR (banked) instructionsPeter Maydell
Starting with the ARMv7 Virtualization Extensions, the A32 and T32 instruction sets provide instructions "MSR (banked)" and "MRS (banked)" which can be used to access registers for a mode other than the current one: * R<m>_<mode> * ELR_hyp * SPSR_<mode> Implement the missing instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1456762734-23939-1-git-send-email-peter.maydell@linaro.org
2016-03-04target-arm: implement setendPaolo Bonzini
Since this is not a high-performance path, just use a helper to flip the E bit and force a lookup in the hash table since the flags have changed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell
Raw CPSR writes should skip the architectural checks for whether we're allowed to set the A or F bits and should also not do the switching of register banks if the mode changes. Handle this inside cpsr_write(), which allows us to drop the "manually set the mode bits to avoid the bank switch" code from all the callsites which are using CPSRWriteRaw. This fixes a bug in 32-bit KVM handling where we had forgotten the "manually set the mode bits" part and could thus potentially trash the register state if the mode from the last exit to userspace differed from the mode on this exit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell
Add an argument to cpsr_write() to indicate what kind of CPSR write is being requested, since the exact behaviour should differ for the different cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Give CPSR setting on 32-bit exception return its own helperPeter Maydell
The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: UNDEF in the UNPREDICTABLE SRS-from-System casePeter Maydell
Make get_r13_banked() raise an exception at runtime for the corner case of SRS from System mode, so that we can UNDEF it; this brings us in to line with the ARM ARM's set of permitted CONSTRAINED UNPREDICTABLE choices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Combine user-only and softmmu get/set_r13_banked()Peter Maydell
The user-mode versions of get/set_r13_banked() exist just to assert if they're ever called -- the translate time code should never emit calls to them because SRS from user mode always UNDEF. There's no code in the softmmu versions that can't compile in CONFIG_USER_ONLY, and the assertion is not particularly useful, so combine the two functions rather than having completely split versions under ifdefs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell
Move get/set_r13_banked() from helper.c to op_helper.c. This will let us add exception-raising code to them, and also puts them in the same file as get/set_user_reg(), which makes some conceptual sense. (The original reason for the helper.c/op_helper.c split was that only op_helper.c had access to the CPU env pointer; this distinction has not been true for a long time, though, and so the split is now rather arbitrary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Fix handling of SCR.SMDPeter Maydell
We weren't quite implementing the handling of SCR.SMD correctly. The condition governing whether the SMD bit should apply only for NS state is "is EL3 is AArch32", not "is the current EL AArch32". Fix the condition, and clarify the comment both to reflect this and to expand slightly on what's going on for the v7-no-Virtualization case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-11target-arm: Implement checking of fired watchpointSergey Fedorov
ARM stops before access to a location covered by watchpoint. Also, QEMU watchpoint fire is not necessarily an architectural watchpoint match. Unfortunately, that is hardly possible to ignore a fired watchpoint in debug exception handler. So move watchpoint check from debug exception handler to the dedicated watchpoint checking callback. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1454256948-10485-3-git-send-email-serge.fdrv@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell
System registers might have access requirements which need to be described via a CPAccessFn and which differ for reads and writes. For this to be possible we need to pass the access function a parameter to tell it whether the access being checked is a read or a write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-6-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM modePeter Maydell
The architecture requires that for an exception return to AArch32 the low bits of ELR_ELx are ignored when the PC is set from them: * if returning to Thumb mode, ignore ELR_ELx[0] * if returning to ARM mode, ignore ELR_ELx[1:0] We were only squashing bit 0; also squash bit 1 if the SPSR T bit indicates this is a return to ARM code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement remaining illegal return event checksPeter Maydell
We already implement almost all the checks for the illegal return events from AArch64 state described in the ARM ARM section D1.11.2. Add the two missing ones: * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0 * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1 (We don't implement external debug, so the case of "debug state exit from EL0 using AArch64 state to EL0 using AArch32 state" doesn't apply for QEMU.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Handle exception return from AArch64 to non-EL0 AArch32Peter Maydell
Remove the assumptions that the AArch64 exception return code was making about a return to AArch32 always being a return to EL0. This includes pulling out the illegal-SPSR checks so we can apply them for return to 32 bit as well as return to 64-bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-18target-arm: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1449505425-32022-3-git-send-email-peter.maydell@linaro.org
2016-01-15target-arm: Use the right MMU index in arm_regime_using_lpae_formatAlvise Rigo
arm_regime_using_lpae_format checks whether the LPAE extension is used for stage 1 translation regimes. MMU indexes not exclusively of a stage 1 regime won't work with this method. In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann
Qemu does not generally perform alignment checks. However, the ARM ARM requires implementation of alignment exceptions for a number of cases including LDREX, and Windows-on-ARM relies on this. This change adds plumbing to enable alignment checks on loads using MO_ALIGN, a do_unaligned_access hook to raise the exception (data abort), and uses the new aligned loads in LDREX (for all but single-byte loads). Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1449167808-5656-1-git-send-email-Andrew.Baumann@microsoft.com [PMM: set WnR bits in syndrome and FSR as appropriate] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-11-10target-arm: Fix gdb singlestep handling in arm_debug_excp_handler()Sergey Fedorov
Do not raise a CPU exception if no CPU breakpoint has fired, since singlestep is also done by generating a debug internal exception. This fixes a bug with singlestepping in gdbstub. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1446726361-18328-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-11-03target-arm: Add and use symbolic names for register banksSoren Brinkmann
Add BANK_<cpumode> #defines to index banked registers. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-15-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Route S2 MMU faults to EL2Edgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-14-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias
Add support for applying S2 translation to 64bit S1 page-table walks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-12-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias
Introduce ARMMMUFaultInfo to propagate MMU Fault information across the MMU translation code path. This is in preparation for adding Stage-2 translation. No functional changes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov
A QEMU breakpoint match is not definitely an architectural breakpoint match. If an exception is generated unconditionally during translation, it is hardly possible to ignore it in the debug exception handler. Generate a call to a helper to check CPU breakpoints and raise an exception only if any breakpoint matches architecturally. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Fix GDB breakpoint handlingSergey Fedorov
GDB breakpoints have higher priority so they have to be checked first. Should GDB breakpoint match, just return from the debug exception handler. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-08-25target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell
Some coprocessor register access functions need to be able to report "trap to EL3 with an 'uncategorized' syndrome"; add the necessary CPAccessResult enum and handling for it. I don't currently know of any registers that need to trap to EL2 with the 'uncategorized' syndrome, but adding the _EL2 enum as well is trivial and fills in what would otherwise be an odd gap in the handling. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1437751263-21913-4-git-send-email-peter.maydell@linaro.org
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell
Currently we use DISAS_WFE for both WFE and YIELD instructions. This is functionally correct because at the moment both of them are implemented as "yield this CPU back to the top level loop so another CPU has a chance to run". However it's rather confusing that YIELD ends up calling HELPER(wfe), and if we ever want to implement real behaviour for WFE and SEV it's likely to trip us up. Split out the yield codepath to use DISAS_YIELD and a new HELPER(yield) function, and have HELPER(wfe) call HELPER(yield). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1435672316-3311-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2015-06-15arm: Refactor get_phys_addr FSR return mechanismPeter Crosthwaite
Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a209e3d8ae00cda55260c970891f520210e26bad.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Correct check for non-EL3Edgar E. Iglesias
This fixes a compile warning from clang 3.5 (the assertion could never fire). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1432881807-18164-2-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: John Snow <jsnow@redhat.com> [PMM: added note in commit message that this is fixing a build warning] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Add WFx instruction trap supportGreg Bellows
Add support for trapping WFI and WFE instructions to the proper EL when SCTLR/SCR/HCR settings apply. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: removed unnecessary tweaking of syn_wfx() prototype; use raise_exception(); don't trap on WFE (and add comment explaining why not); remove unnecessary ARM_FEATURE checks; trap to EL3, not EL1, if in S-EL0 and SCTLR check fires] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Don't halt on WFI unless we don't have any workPeter Maydell
Just NOP the WFI instruction if we have work to do. This doesn't make much difference currently (though it does avoid jumping out to the top level loop and immediately restarting), but the distinction between "halt" and "don't halt" will become more important when the decision to halt requires us to trap to a higher exception level instead. Suggested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Allow cp access functions to indicate traps to EL2 or EL3Peter Maydell
Some coprocessor access functions will need to indicate that the instruction should trap to EL2 or EL3 rather than the default target exception level; add corresponding CPAccessResult enum entries and handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Make raise_exception() take syndrome and target ELPeter Maydell
Rather than making every caller of raise_exception set the syndrome and target EL by hand, make these arguments to raise_exception() and have that do the job. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Set exception target EL in tlb_fillPeter Maydell
Set the exception target EL for MMU faults in tlb_fill. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell
Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Set correct syndrome for faults on MSR DAIF*, immPeter Maydell
If the SCTLR.UMA trap bit is set then attempts by EL0 to update the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" instructions will raise an exception. We were failing to set the syndrome information for this exception, which meant that it would be reported as a repeat of whatever the previous exception was. Set the correct syndrome information. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Extend helpers to route exceptionsGreg Bellows
Updated the various helper routines to set the target EL as needed using a dedicated function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-3-git-send-email-greg.bellows@linaro.org [PMM: Also set target_el in fault cases in access_check_cp_reg()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows
Add a CPU state exception target EL field that will be used for communicating the EL to which an exception should be routed. Add a disassembly context field for tracking the EL3 architecture needed for determining the target exception EL. Add a target EL argument to the generic exception helper for callers to specify the EL to which the exception should be routed. Extended the helper to set the newly added CPU state exception target el. Added a function for setting the target exception EL and updated calls to helpers to call it. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-26target-arm: Check watchpoints against CPU security statePeter Maydell
Fix a TODO in bp_wp_matches() now that we have a function for testing whether the CPU is currently in Secure mode or not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-26target-arm: Use attribute info to handle user-only watchpointsPeter Maydell
Now that we have memory access attribute information in the watchpoint checking code, we can correctly implement handling of watchpoints which should match only on userspace accesses, where LDRT/STRT/LDT/STT from EL1 are treated as userspace accesses. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-02-13target-arm: Add 32/64-bit register syncGreg Bellows
Add AArch32 to AArch64 register sychronization functions. Replace manual register synchronization with new functions in aarch64_cpu_do_interrupt() and HELPER(exception_return)(). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1423736974-14254-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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