aboutsummaryrefslogtreecommitdiff
path: root/target-arm/helper.c
AgeCommit message (Expand)Author
2016-11-07Fix corruption of CPSR when SCTLR.EE is setJulian Brown
2016-10-24target-arm: Implement new HLT trap for semihostingPeter Maydell
2016-10-17target-arm: Add trace events for the generic timersPeter Maydell
2016-10-17target-arm: Implement dummy MDCCINT_EL1Peter Maydell
2016-10-17target-arm: Infrastucture changes to enable handling of tagged address loadin...Thomas Hanson
2016-09-16tcg: Merge GETPC and GETRARichard Henderson
2016-09-13arm: spelling fix: mismatchMichael Tokarev
2016-07-14target-arm: Add missed AArch32 TLBI sytem registersSergey Sorokin
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic
2016-06-17target-arm: Provide hook to tell GICv3 about changes of security statePeter Maydell
2016-06-14target-arm: Fix reset and migration of TTBCR(S)Peter Maydell
2016-06-06target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translationSergey Sorokin
2016-06-06target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()Peter Maydell
2016-06-06target-arm: Add the HSTR_EL2 registerAlistair Francis
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
2016-05-19arm: move arm_log_exception into .c filePaolo Bonzini
2016-05-12target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell
2016-05-12target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin
2016-05-12target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin
2016-04-04target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell
2016-04-04target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell
2016-04-04target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell
2016-03-16target-arm: Fix translation level on early translation faultsSergey Sorokin
2016-03-04target-arm: implement SCTLR.EEPeter Crosthwaite
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini
2016-03-04target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell
2016-02-26target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell
2016-02-26target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias
2016-02-26target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell
2016-02-26target-arm: Fix handling of SDCR for 32-bit codePeter Maydell
2016-02-26target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell
2016-02-26target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell
2016-02-26target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell
2016-02-26target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell
2016-02-26target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell
2016-02-26target-arm: Add comment about not implementing NSACR.RFRPeter Maydell
2016-02-26target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell
2016-02-26target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell
2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis
2016-02-18target-arm: Move bank_number() into internals.hPeter Maydell
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell
2016-02-18target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell
2016-02-18target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell
2016-02-18target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell
2016-02-18target-arm: correct CNTFRQ access rightsPeter Maydell
2016-02-11target-arm: Implement NSACR trapping behaviourPeter Maydell
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-18 11:14:36 +0000