Age | Commit message (Expand) | Author |
2016-06-17 | target-arm: Provide hook to tell GICv3 about changes of security state | Peter Maydell |
2016-06-14 | target-arm: Fix reset and migration of TTBCR(S) | Peter Maydell |
2016-06-06 | target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation | Sergey Sorokin |
2016-06-06 | target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64() | Peter Maydell |
2016-06-06 | target-arm: Add the HSTR_EL2 register | Alistair Francis |
2016-05-19 | cpu: move exec-all.h inclusion out of cpu.h | Paolo Bonzini |
2016-05-19 | arm: move arm_log_exception into .c file | Paolo Bonzini |
2016-05-12 | target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writes | Peter Maydell |
2016-05-12 | target-arm: Fix descriptor address masking in ARM address translation | Sergey Sorokin |
2016-05-12 | target-arm: Stage 2 permission fault was fixed in AArch32 state | Sergey Sorokin |
2016-04-04 | target-arm: Make the 64-bit version of VTCR do the migration | Peter Maydell |
2016-04-04 | target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3 | Peter Maydell |
2016-04-04 | target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs | Peter Maydell |
2016-03-16 | target-arm: Fix translation level on early translation faults | Sergey Sorokin |
2016-03-04 | target-arm: implement SCTLR.EE | Peter Crosthwaite |
2016-03-04 | target-arm: implement SCTLR.B, drop bswap_code | Paolo Bonzini |
2016-03-04 | target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode | Peter Maydell |
2016-02-26 | target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF | Peter Maydell |
2016-02-26 | target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW | Edgar E. Iglesias |
2016-02-26 | target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps | Peter Maydell |
2016-02-26 | target-arm: Fix handling of SDCR for 32-bit code | Peter Maydell |
2016-02-26 | target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 | Peter Maydell |
2016-02-26 | target-arm: Make mode switches from Hyp via CPS and MRS illegal | Peter Maydell |
2016-02-26 | target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL | Peter Maydell |
2016-02-26 | target-arm: Forbid mode switch to Mon from Secure EL1 | Peter Maydell |
2016-02-26 | target-arm: Add Hyp mode checks to bad_mode_switch() | Peter Maydell |
2016-02-26 | target-arm: Add comment about not implementing NSACR.RFR | Peter Maydell |
2016-02-26 | target-arm: In cpsr_write() ignore mode switches from User mode | Peter Maydell |
2016-02-26 | target-arm: Raw CPSR writes should skip checks and bank switching | Peter Maydell |
2016-02-26 | target-arm: Add write_type argument to cpsr_write() | Peter Maydell |
2016-02-18 | target-arm: Add PMUSERENR_EL0 register | Alistair Francis |
2016-02-18 | target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers | Alistair Francis |
2016-02-18 | target-arm: Add the pmceid0 and pmceid1 registers | Alistair Francis |
2016-02-18 | target-arm: Move bank_number() into internals.h | Peter Maydell |
2016-02-18 | target-arm: Move get/set_r13_banked() to op_helper.c | Peter Maydell |
2016-02-18 | target-arm: Report correct syndrome for FPEXC32_EL2 traps | Peter Maydell |
2016-02-18 | target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA traps | Peter Maydell |
2016-02-18 | target-arm: Implement MDCR_EL2.TDRA traps | Peter Maydell |
2016-02-18 | target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps | Peter Maydell |
2016-02-18 | target-arm: correct CNTFRQ access rights | Peter Maydell |
2016-02-11 | target-arm: Implement NSACR trapping behaviour | Peter Maydell |
2016-02-11 | target-arm: Add isread parameter to CPAccessFns | Peter Maydell |
2016-02-11 | target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR | Peter Maydell |
2016-02-11 | target-arm: Implement MDCR_EL3 and SDCR | Peter Maydell |
2016-02-03 | target-arm: Implement the S2 MMU inputsize > pamax check | Edgar E. Iglesias |
2016-02-03 | target-arm: Rename check_s2_startlevel to check_s2_mmu_setup | Edgar E. Iglesias |
2016-02-03 | target-arm: Apply S2 MMU startlevel table size check to AArch64 | Edgar E. Iglesias |
2016-02-03 | target-arm: Make various system registers visible to EL3 | Peter Maydell |
2016-01-21 | target-arm: Implement FPEXC32_EL2 system register | Peter Maydell |
2016-01-21 | target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target | Peter Maydell |