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2016-05-19arm: move arm_log_exception into .c filePaolo Bonzini
Avoid need for qemu/log.h inclusion, and make the function static too. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-12target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell
The TCR_EL2 and TCR_EL3 regdefs were incorrectly using the vmsa_tcr_el1_write function for writes. Since these registers don't have the A1 bit that TCR_EL1 does, we don't need to do a tlb_flush() when they are written. Remove the unnecessary .writefn and also the harmless but unneeded .raw_writefn and .resetfn definitions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org>
2016-05-12target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin
There is a bug in ARM address translation regime with a long-descriptor format. On the descriptor reading its address is formed from an index which is a part of the input address. And on the first iteration this index is incorrectly masked with 'grainsize' mask. But it can be wider according to pseudo-code. On the other hand on the iterations other than first the descriptor address is formed from the previous level descriptor by masking with 'descaddrmask' value. It always clears just 12 lower bits, but it must clear 'grainsize' lower bits instead according to pseudo-code. The patch fixes both cases. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1460996853-22117-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-05-12target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin
As described in AArch32.CheckS2Permission an instruction fetch fails if XN bit is set or there is no read permission for the address. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1461002400-3187-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-04-04target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell
Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the 64-bit version, as is usual. (This has no particular effect now unless the guest wrote to the high RES0 bits of VTCR_EL2.) Add a comment about why it's OK that we don't have the various accessor functions that the EL1 TCR regdefs do. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1459435778-5526-4-git-send-email-peter.maydell@linaro.org
2016-04-04target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell
The regdefs for the ESR_EL2 and ESR_EL3 system registers should not be marked as ARM_CP_ALIAS, because these are the master copies; the DFSR regdef in vmsa_pmsa_cp_reginfo[] is marked as an alias. Remove the ALIAS tags so that these registers are correctly migrated. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.rog> Message-id: 1459435778-5526-3-git-send-email-peter.maydell@linaro.org
2016-04-04target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell
The regdef for SCTRL_EL3 was incorrectly marked as being an ARM_CP_ALIAS, with the remark that this was because the 32-bit definition would take care of reset and migration. However the intention for banked registers as documented in the comment in add_cpreg_to_hashtable() is: * 2) If ARMv8 is enabled then we can count on a 64-bit version * taking care of the secure bank. This requires that separate * 32 and 64-bit definitions are provided. and so it marks the 32-bit secure banked version as an alias. This results in the sctlr_s/sctlr_el[3] field never being reset or migrated for a 64-bit CPU with EL3 enabled. Fix this by removing the ARM_CP_ALIAS annotation from SCTLR_EL3. Since this means it now needs a real reset value, move the regdef into the same place that we define the 32-bit SCTLR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1459435778-5526-2-git-send-email-peter.maydell@linaro.org
2016-03-16target-arm: Fix translation level on early translation faultsSergey Sorokin
Qemu reports translation fault on 1st level instead of 0th level in case of AArch64 address translation if the translation table walk is disabled or the address is in the gap between the two regions. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1457527503-25958-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement SCTLR.EEPeter Crosthwaite
Implement SCTLR.EE bit which controls data endianess for exceptions and page table translations. SCTLR.EE is mirrored to the CPSR.E bit on exception entry. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini
bswap_code is a CPU property of sorts ("is the iside endianness the opposite way round to TARGET_WORDS_BIGENDIAN?") but it is not the actual CPU state involved here which is SCTLR.B (set for BE32 binaries, clear for BE8). Replace bswap_code with SCTLR.B, and pass that to arm_ld*_code. The next patches will make data fetches honor both SCTLR.B and CPSR.E appropriately. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PC changes: * rebased on master (Jan 2016) * s/TARGET_USER_ONLY/CONFIG_USER_ONLY * Use bswap_code() for disas_set_info() instead of raw sctlr_b ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell
In helper.c the expression (env->uncached_cpsr & CPSR_M) != CPSR_USER is always true; the right hand side was supposed to be ARM_CPU_MODE_USR (an error in commit cb01d391). Since the incorrect expression was always true, this just meant that commit cb01d391 had no effect. However simply changing the RHS here would reveal a logic error: if the mode is USR we wish to completely ignore the attempt to set the mode bits, which means that we must clear the CPSR_M bits from mask to avoid the uncached_cpsr bits being updated at the end of the function. Move the condition into the correct place in the code, fix its RHS constant, and add a comment about the fact that we must be doing a gdbstub write if we're in user mode. Fixes: https://bugs.launchpad.net/qemu/+bug/1550503 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456764438-30015-1-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell
The v8 ARM ARM defines that unused spaces in the ID_AA64* system register ranges are Reserved and must RAZ, rather than being UNDEF. Implement this. In particular, ARM v8.2 adds a new feature register ID_AA64MMFR2, and newer versions of the Linux kernel will attempt to read this, which causes them not to boot up on versions of QEMU missing this fix. Since the encoding .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6 is actually defined in ARMv8 (as ID_MMFR4), we give it an entry in the ARMCPU struct so CPUs can override it, though since none do this too will just RAZ. Cc: qemu-stable@nongnu.org Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455890863-11203-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org>
2016-02-26target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias
Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW due to the register not having any underlying state. This fixes an issue with booting KVM enabled kernels when EL2 is on. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1456490739-19343-1-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-26target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell
Implement the performance monitor register traps controlled by MDCR_EL3.TPM and MDCR_EL2.TPM. Most of the performance registers already have an access function to deal with the user-enable bit, and the TPM checks can be added there. We also need a new access function which only implements the TPM checks for use by the few not-EL0-accessible registers and by PMUSERENR_EL0 (which is always EL0-readable). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455892784-11328-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
2016-02-26target-arm: Fix handling of SDCR for 32-bit codePeter Maydell
Fix two issues with our implementation of the SDCR: * it is only present from ARMv8 onwards * it does not contain several of the trap bits present in its 64-bit counterpart the MDCR_EL3 Put the register description in the right place so that it does not get enabled for ARMv7 and earlier, and give it a write function so that we can mask out the bits which should not be allowed to have an effect if EL3 is 32-bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455892784-11328-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
2016-02-26target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell
If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to NonSecure PL1 modes are illegal mode changes. Implement this check in bad_mode_switch(). (We don't currently implement HCR.TGE, but this is the only missing check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the rest of the HCR.TGE checks can be added later as necessary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-12-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell
Mode switches from Hyp to any other mode via the CPS and MRS instructions are illegal mode switches (though obviously switching via exception return is valid). Add this check to bad_mode_switch(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-11-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are given architected behaviour: * the mode field is unchanged * PSTATE.IL is set (so any subsequent instructions will UNDEF) * any other CPSR fields are written to as normal This is pretty much the same behaviour we picked for our UNPREDICTABLE handling, with the exception that for v8 we need to set the IL bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-10-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell
In v8 trying to switch mode to Mon from Secure EL1 is an illegal mode switch. (In v7 this is impossible as all secure modes except User are at EL3.) We can handle this case by making a switch to Mon valid only if the current EL is 3, which then gives the correct answer whether EL3 is AArch32 or AArch64. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-9-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell
We don't actually support Hyp mode yet, but add the correct checks for it to the bad_mode_switch() function for completeness. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-8-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add comment about not implementing NSACR.RFRPeter Maydell
QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell
The only case where we can attempt a cpsr_write() mode switch from User is from the gdbstub; all other cases are handled in the calling code (notably translate.c). Architecturally attempts to alter the mode bits from user mode are simply ignored (and not treated as a bad mode switch, which in v8 sets CPSR.IL). Make mode switches from User ignored in cpsr_write() as well, for consistency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-6-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell
Raw CPSR writes should skip the architectural checks for whether we're allowed to set the A or F bits and should also not do the switching of register banks if the mode changes. Handle this inside cpsr_write(), which allows us to drop the "manually set the mode bits to avoid the bank switch" code from all the callsites which are using CPSRWriteRaw. This fixes a bug in 32-bit KVM handling where we had forgotten the "manually set the mode bits" part and could thus potentially trash the register state if the mode from the last exit to userspace differed from the mode on this exit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell
Add an argument to cpsr_write() to indicate what kind of CPSR write is being requested, since the exact behaviour should differ for the different cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis
The Linux kernel accesses this register early in its setup. Signed-off-by: Christopher Covington <christopher.covington@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: b30d536cb16ec57b4412172bb6dbc3f00d293e7d.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 50deeafb24958a5b6d7f594b5dda399a022c0e5b.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Message-id: da0563119a9f56fd5fbdc26e7ed19a8a8457c5b9.1455060548.git.alistair.francis@xilinx.com [PMM: Use 0 for PMCEID0 values for A15 and A57 since our PMU does not currently implement any events.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Move bank_number() into internals.hPeter Maydell
Move bank_number()'s implementation into internals.h, so it's available in the user-mode-only compile as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell
Move get/set_r13_banked() from helper.c to op_helper.c. This will let us add exception-raising code to them, and also puts them in the same file as get/set_user_reg(), which makes some conceptual sense. (The original reason for the helper.c/op_helper.c split was that only op_helper.c had access to the CPU env pointer; this distinction has not been true for a long time, though, and so the split is now rather arbitrary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell
Implement the debug register traps controlled by MDCR_EL2.TDA and MDCR_EL3.TDA. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell
Implement trapping of the "debug ROM" registers, which are controlled by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell
Implement the traps to EL2 and EL3 controlled by the bits MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap accesses to the "powerdown debug" registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: correct CNTFRQ access rightsPeter Maydell
Correct some corner cases we were getting wrong for CNTFRQ access rights: * should UNDEF from 32-bit Secure EL1 * only writable from the highest implemented exception level, which might not be EL1 now To clarify the code, provide a new utility function arm_highest_el() which returns the highest implemented exception level. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-11target-arm: Implement NSACR trapping behaviourPeter Maydell
Implement some corner cases of the behaviour of the NSACR register on ARMv8: * if EL3 is AArch64 then accessing the NSACR from Secure EL1 with AArch32 should trap to EL3 * if EL3 is not present or is AArch64 then reads from NS EL1 and NS EL2 return constant 0xc00 It would in theory be possible to implement all these with a single reginfo definition, but for clarity we use three separate definitions for the three cases and install the right one based on the CPU feature flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-7-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell
System registers might have access requirements which need to be described via a CPAccessFn and which differ for reads and writes. For this to be possible we need to pass the access function a parameter to tell it whether the access being checked is a read or a write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-6-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell
The registers MVBAR and SCR should have the behaviour of trapping to EL3 if accessed from Secure EL1, but we were incorrectly implementing them to UNDEF (which would trap to EL1). Fix this by using the new access_trap_aa32s_el1() access function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-4-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Implement MDCR_EL3 and SDCRPeter Maydell
Implement the MDCR_EL3 register (which is SDCR for AArch32). For the moment we implement it as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-3-git-send-email-peter.maydell@linaro.org
2016-02-03target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias
Implement the inputsize > pamax check for Stage 2 translations. This is CONSTRAINED UNPREDICTABLE and we choose to fault. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1453932970-14576-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias
Rename check_s2_startlevel to check_s2_mmu_setup in preparation for additional checks. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1453932970-14576-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias
The S2 starting level table size check applies to both AArch32 and AArch64. Move it to common code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1453932970-14576-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03target-arm: Make various system registers visible to EL3Peter Maydell
The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ, SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from EL3 even if the CPU has no EL2 (unlike some others which are RES0 from EL3 in that configuration). Move them from el2_cp_reginfo[] to v8_cp_reginfo[] so they are always present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453227802-9991-1-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: Implement FPEXC32_EL2 system registerPeter Maydell
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453132414-8127-1-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell
The entry offset when taking an exception to AArch64 from a lower exception level may be 0x400 or 0x600. 0x400 is used if the implemented exception level immediately lower than the target level is using AArch64, and 0x600 if it is using AArch32. We were incorrectly implementing this as checking the exception level that the exception was taken from. (The two can be different if for example we take an exception from EL0 to AArch64 EL3; we should in this case be checking EL2 if EL2 is implemented, and EL1 if EL2 is not implemented.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell
Handling of semihosting calls should depend on the register width of the calling code, not on that of any higher exception level, so we need to identify and handle semihosting calls before we decide whether to deliver the exception as an entry to AArch32 or AArch64. (EXCP_SEMIHOST is also an "internal exception" so it has no target exception level in the first place.) This will allow AArch32 EL1 code to use semihosting calls when running under an AArch64 EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell
If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be taken to an exception level which is running AArch32 (if only EL0 and EL1 are present then EL1 must be AArch64 and all exceptions are taken to AArch64). To support this we need to have a single implementation of the CPU do_interrupt() method which can handle both 32 and 64 bit exception entry. Pull the common parts of aarch64_cpu_do_interrupt() and arm_cpu_do_interrupt() out into a new function which calls either the AArch32 or AArch64 specific entry code once it has worked out which one is needed. We temporarily special-case the handling of EXCP_SEMIHOST to avoid an assertion in arm_el_is_aa64(); the next patch will pull all the semihosting handling out to the arm_cpu_do_interrupt() level (since semihosting semantics depend on the register width of the calling code, not on that of any higher EL). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell
Move the aarch64_cpu_do_interrupt() function to helper.c. We want to be able to call this from code that isn't AArch64-only, and the move allows us to avoid awkward #ifdeffery at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Support multiple address spaces in page table walksPeter Maydell
If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell
Implement cpu_get_phys_page_attrs_debug instead of cpu_get_phys_page_debug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-18target-arm: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1449505425-32022-3-git-send-email-peter.maydell@linaro.org