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2016-02-26target-arm: Add write_type argument to cpsr_write()Peter Maydell
Add an argument to cpsr_write() to indicate what kind of CPSR write is being requested, since the exact behaviour should differ for the different cases. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis
The Linux kernel accesses this register early in its setup. Signed-off-by: Christopher Covington <christopher.covington@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: b30d536cb16ec57b4412172bb6dbc3f00d293e7d.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 50deeafb24958a5b6d7f594b5dda399a022c0e5b.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Nathan Rossi <nathan@nathanrossi.com> Message-id: da0563119a9f56fd5fbdc26e7ed19a8a8457c5b9.1455060548.git.alistair.francis@xilinx.com [PMM: Use 0 for PMCEID0 values for A15 and A57 since our PMU does not currently implement any events.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-18target-arm: Move bank_number() into internals.hPeter Maydell
Move bank_number()'s implementation into internals.h, so it's available in the user-mode-only compile as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell
Move get/set_r13_banked() from helper.c to op_helper.c. This will let us add exception-raising code to them, and also puts them in the same file as get/set_user_reg(), which makes some conceptual sense. (The original reason for the helper.c/op_helper.c split was that only op_helper.c had access to the CPU env pointer; this distinction has not been true for a long time, though, and so the split is now rather arbitrary.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell
If access to FPEXC32_EL2 is trapped by CPTR_EL2.TFP or CPTR_EL3.TFP, this should be reported with a syndrome register indicating an FP access trap, not one indicating a system register access trap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell
Implement the debug register traps controlled by MDCR_EL2.TDA and MDCR_EL3.TDA. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell
Implement trapping of the "debug ROM" registers, which are controlled by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell
Implement the traps to EL2 and EL3 controlled by the bits MDCR_EL2.TDOSA MDCR_EL3.TDOSA. These can configurably trap accesses to the "powerdown debug" registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
2016-02-18target-arm: correct CNTFRQ access rightsPeter Maydell
Correct some corner cases we were getting wrong for CNTFRQ access rights: * should UNDEF from 32-bit Secure EL1 * only writable from the highest implemented exception level, which might not be EL1 now To clarify the code, provide a new utility function arm_highest_el() which returns the highest implemented exception level. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-02-11target-arm: Implement NSACR trapping behaviourPeter Maydell
Implement some corner cases of the behaviour of the NSACR register on ARMv8: * if EL3 is AArch64 then accessing the NSACR from Secure EL1 with AArch32 should trap to EL3 * if EL3 is not present or is AArch64 then reads from NS EL1 and NS EL2 return constant 0xc00 It would in theory be possible to implement all these with a single reginfo definition, but for clarity we use three separate definitions for the three cases and install the right one based on the CPU feature flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-7-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell
System registers might have access requirements which need to be described via a CPAccessFn and which differ for reads and writes. For this to be possible we need to pass the access function a parameter to tell it whether the access being checked is a read or a write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-6-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell
The registers MVBAR and SCR should have the behaviour of trapping to EL3 if accessed from Secure EL1, but we were incorrectly implementing them to UNDEF (which would trap to EL1). Fix this by using the new access_trap_aa32s_el1() access function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-4-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Implement MDCR_EL3 and SDCRPeter Maydell
Implement the MDCR_EL3 register (which is SDCR for AArch32). For the moment we implement it as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-3-git-send-email-peter.maydell@linaro.org
2016-02-03target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias
Implement the inputsize > pamax check for Stage 2 translations. This is CONSTRAINED UNPREDICTABLE and we choose to fault. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1453932970-14576-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias
Rename check_s2_startlevel to check_s2_mmu_setup in preparation for additional checks. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1453932970-14576-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias
The S2 starting level table size check applies to both AArch32 and AArch64. Move it to common code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1453932970-14576-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03target-arm: Make various system registers visible to EL3Peter Maydell
The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ, SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from EL3 even if the CPU has no EL2 (unlike some others which are RES0 from EL3 in that configuration). Move them from el2_cp_reginfo[] to v8_cp_reginfo[] so they are always present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453227802-9991-1-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: Implement FPEXC32_EL2 system registerPeter Maydell
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3, and allows those exception levels to read and write the FPEXC register for a lower exception level that is using AArch32. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1453132414-8127-1-git-send-email-peter.maydell@linaro.org
2016-01-21target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell
The entry offset when taking an exception to AArch64 from a lower exception level may be 0x400 or 0x600. 0x400 is used if the implemented exception level immediately lower than the target level is using AArch64, and 0x600 if it is using AArch32. We were incorrectly implementing this as checking the exception level that the exception was taken from. (The two can be different if for example we take an exception from EL0 to AArch64 EL3; we should in this case be checking EL2 if EL2 is implemented, and EL1 if EL2 is not implemented.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell
Handling of semihosting calls should depend on the register width of the calling code, not on that of any higher exception level, so we need to identify and handle semihosting calls before we decide whether to deliver the exception as an entry to AArch32 or AArch64. (EXCP_SEMIHOST is also an "internal exception" so it has no target exception level in the first place.) This will allow AArch32 EL1 code to use semihosting calls when running under an AArch64 EL3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-01-21target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell
If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be taken to an exception level which is running AArch32 (if only EL0 and EL1 are present then EL1 must be AArch64 and all exceptions are taken to AArch64). To support this we need to have a single implementation of the CPU do_interrupt() method which can handle both 32 and 64 bit exception entry. Pull the common parts of aarch64_cpu_do_interrupt() and arm_cpu_do_interrupt() out into a new function which calls either the AArch32 or AArch64 specific entry code once it has worked out which one is needed. We temporarily special-case the handling of EXCP_SEMIHOST to avoid an assertion in arm_el_is_aa64(); the next patch will pull all the semihosting handling out to the arm_cpu_do_interrupt() level (since semihosting semantics depend on the register width of the calling code, not on that of any higher EL). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell
Move the aarch64_cpu_do_interrupt() function to helper.c. We want to be able to call this from code that isn't AArch64-only, and the move allows us to avoid awkward #ifdeffery at the callsite. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Support multiple address spaces in page table walksPeter Maydell
If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-21target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell
Implement cpu_get_phys_page_attrs_debug instead of cpu_get_phys_page_debug. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-01-18target-arm: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 1449505425-32022-3-git-send-email-peter.maydell@linaro.org
2016-01-15target-arm: Use the right MMU index in arm_regime_using_lpae_formatAlvise Rigo
arm_regime_using_lpae_format checks whether the LPAE extension is used for stage 1 translation regimes. MMU indexes not exclusively of a stage 1 regime won't work with this method. In case of ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1, offset these values by ARMMMUIdx_S1NSE0 to get the right index indicating a stage 1 translation regime. Rename also the function to arm_s1_regime_using_lpae_format and update the comments to reflect the change. Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com> Message-id: 1452854262-19550-1-git-send-email-a.rigo@virtualopensystems.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann
Qemu does not generally perform alignment checks. However, the ARM ARM requires implementation of alignment exceptions for a number of cases including LDREX, and Windows-on-ARM relies on this. This change adds plumbing to enable alignment checks on loads using MO_ALIGN, a do_unaligned_access hook to raise the exception (data abort), and uses the new aligned loads in LDREX (for all but single-byte loads). Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1449167808-5656-1-git-send-email-Andrew.Baumann@microsoft.com [PMM: set WnR bits in syndrome and FSR as appropriate] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-11-24target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8Peter Maydell
In an LPAE format descriptor in ARMv8 the address field extends up to bit 47, not just bit 39. Correct the masking so we don't give incorrect results if the output address size is greater than 40 bits, as it can be for AArch64. (Note that we don't yet support the new-in-v8 Address Size fault which should be generated if any translation table entry or TTBR contains an address with non-zero bits above the most significant bit of the maximum output address size.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1448029971-9875-1-git-send-email-peter.maydell@linaro.org
2015-11-03target-arm: Add and use symbolic names for register banksSoren Brinkmann
Add BANK_<cpumode> #defines to index banked registers. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-15-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias
Add support for applying S2 translation to 32bit S1 page-table walks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-13-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias
Add support for applying S2 translation to 64bit S1 page-table walks. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-12-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias
Introduce ARMMMUFaultInfo to propagate MMU Fault information across the MMU translation code path. This is in preparation for adding Stage-2 translation. No functional changes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias
Avoid inline for get_phys_addr() to prepare for future recursive use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-10-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-9-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias
The starting level for S2 pagetable walks is computed differently from the S1 starting level. Implement the S2 variant. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-8-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias
Rename granule_sz to stride to better match the reference manuals. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias
Remove the tsz variable and introduce inputsize. This simplifies the code a little and makes it easier to compare with the reference manuals. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias
Add support for AArch32 S2 negative t0sz. In preparation for using 40bit IPAs on AArch32. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-5-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias
Move declaration of t0sz and t1sz to the top of the function avoiding a mix of code and variable declarations. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-4-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias
Make t0sz and t1sz signed integers to match tsz and to make it easier to implement support for AArch32 negative t0sz. t1sz is changed for consistensy. No functional change. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add HPFAR_EL2Edgar E. Iglesias
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-27target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Add MDCR_EL2Sergey Fedorov
Add the MDCR_EL2 register. We don't implement any of the debug-related traps this register controls yet, so currently it simply reads back as written. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1444383794-16767-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message; moved non-dummy definition from debug_cp_reginfo to el2_cp_reginfo.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista
Added oslar_write function to OSLAR_EL1 sysreg, using a status variable in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked to the newly added read-only OSLSR_EL1 register. Linux reads from this register during its suspend/resume procedure. Signed-off-by: Davorin Mista <davorin.mista@aggios.com> [PMM: folded a long line and tweaked a comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin
It is incorrect to call arm_el_is_aa64() function for unimplemented EL. This patch fixes several attempts to do so. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: Reworked several of the comments to be more verbose.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin
If any store instruction writes the code inside the same TB after this store insn, the execution of the TB must be stopped to execute new code correctly. As described in ARMv8 manual D3.4.6 self-modifying code must do an IC invalidation to be valid, and an ISB after it. So it's enough to end the TB after ISB instruction on the code translation. Also this TB break is necessary to take any pending interrupts immediately after an ISB (as required by ARMv8 ARM D1.14.4). Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> [PMM: tweaked commit message and comments slightly] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-10-16target-arm: Add missing 'static' attributeStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1443213733-9807-1-git-send-email-sw@weilnetz.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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