Age | Commit message (Expand) | Author |
2015-10-27 | target-arm: Add support for S1 + S2 MMU translations | Edgar E. Iglesias |
2015-10-27 | target-arm: Add S2 translation to 32bit S1 PTWs | Edgar E. Iglesias |
2015-10-27 | target-arm: Add S2 translation to 64bit S1 PTWs | Edgar E. Iglesias |
2015-10-27 | target-arm: Add ARMMMUFaultInfo | Edgar E. Iglesias |
2015-10-27 | target-arm: Avoid inline for get_phys_addr | Edgar E. Iglesias |
2015-10-27 | target-arm: Add support for S2 page-table protection bits | Edgar E. Iglesias |
2015-10-27 | target-arm: Add computation of starting level for S2 PTW | Edgar E. Iglesias |
2015-10-27 | target-arm: lpae: Rename granule_sz to stride | Edgar E. Iglesias |
2015-10-27 | target-arm: lpae: Replace tsz with computed inputsize | Edgar E. Iglesias |
2015-10-27 | target-arm: Add support for AArch32 S2 negative t0sz | Edgar E. Iglesias |
2015-10-27 | target-arm: lpae: Move declaration of t0sz and t1sz | Edgar E. Iglesias |
2015-10-27 | target-arm: lpae: Make t0sz and t1sz signed integers | Edgar E. Iglesias |
2015-10-27 | target-arm: Add HPFAR_EL2 | Edgar E. Iglesias |
2015-10-27 | target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) | Soren Brinkmann |
2015-10-16 | target-arm: Add MDCR_EL2 | Sergey Fedorov |
2015-10-16 | target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs | Davorin Mista |
2015-10-16 | target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL | Sergey Sorokin |
2015-10-16 | target-arm: Break the TB after ISB to execute self-modified code correctly | Sergey Sorokin |
2015-10-16 | target-arm: Add missing 'static' attribute | Stefan Weil |
2015-09-25 | arm: clarify the use of muldiv64() | Laurent Vivier |
2015-09-15 | target-arm: Use new revbit functions | Richard Henderson |
2015-09-14 | target-arm: Add VMPIDR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Break out mpidr_read_val() | Edgar E. Iglesias |
2015-09-14 | target-arm: Add VPIDR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Suppress EPD for S2, EL2 and EL3 translations | Edgar E. Iglesias |
2015-09-14 | target-arm: Suppress TBI for S2 translations | Edgar E. Iglesias |
2015-09-14 | target-arm: Add VTTBR_EL2 | Edgar E. Iglesias |
2015-09-14 | target-arm: Add VTCR_EL2 | Edgar E. Iglesias |
2015-09-11 | tlb: Add "ifetch" argument to cpu_mmu_index() | Benjamin Herrenschmidt |
2015-09-11 | maint: remove / fix many doubled words | Daniel P. Berrange |
2015-09-08 | target-arm: Add AArch64 access to PAR_EL1 | Edgar E. Iglesias |
2015-09-08 | target-arm: Correct opc1 for AT_S12Exx | Edgar E. Iglesias |
2015-09-07 | target-arm: Fix AArch32:AArch64 general-purpose register mapping | Sergey Sorokin |
2015-09-07 | arm: Remove hw_error() usages. | Peter Crosthwaite |
2015-09-07 | target-arm: Improve semihosting debug prints | Christopher Covington |
2015-08-25 | target-arm: Implement AArch64 TLBI operations on IPAs | Peter Maydell |
2015-08-25 | target-arm: Implement missing EL3 TLB invalidate operations | Peter Maydell |
2015-08-25 | target-arm: Implement missing EL2 TLBI operations | Peter Maydell |
2015-08-25 | target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch | Peter Maydell |
2015-08-25 | target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order | Peter Maydell |
2015-08-25 | target-arm: Implement AArch32 ATS1H* operations | Peter Maydell |
2015-08-25 | target-arm: Enable the AArch32 ATS12NSO ops | Peter Maydell |
2015-08-25 | target-arm: Wire up AArch64 EL2 and EL3 address translation ops | Peter Maydell |
2015-08-25 | target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations | Peter Maydell |
2015-08-25 | target-arm: Implement missing ACTLR registers | Peter Maydell |
2015-08-25 | target-arm: Implement missing AFSR registers | Peter Maydell |
2015-08-25 | target-arm: Implement missing AMAIR registers | Peter Maydell |
2015-08-25 | target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers | Peter Maydell |
2015-08-13 | target-arm: Add AArch32 banked register access to secure physical timer | Peter Maydell |
2015-08-13 | target-arm: Add the AArch64 view of the Secure physical timer | Peter Maydell |