Age | Commit message (Expand) | Author |
2014-09-29 | target-arm: Add HCR_EL2 | Edgar E. Iglesias |
2014-09-29 | target-arm: Don't handle c15_cpar changes via tb_flush() | Peter Maydell |
2014-09-29 | target-arm: Implement setting guest breakpoints | Peter Maydell |
2014-09-12 | target-arm: Make *IS TLB maintenance ops affect all CPUs | Peter Maydell |
2014-09-12 | target-arm: Push legacy wildcard TLB ops back into v6 | Peter Maydell |
2014-09-12 | target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 | Peter Maydell |
2014-09-12 | target-arm: Remove comment about MDSCR_EL1 being dummy implementation | Peter Maydell |
2014-09-12 | target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 | Peter Maydell |
2014-09-12 | target-arm: Implement handling of fired watchpoints | Peter Maydell |
2014-09-12 | target-arm: Move extended_addresses_enabled() to internals.h | Peter Maydell |
2014-09-12 | target-arm: Implement setting of watchpoints | Peter Maydell |
2014-08-29 | target-arm: Implement pmccfiltr_write function | Alistair Francis |
2014-08-29 | target-arm: Remove old code and replace with new functions | Alistair Francis |
2014-08-29 | target-arm: Implement pmccntr_sync function | Alistair Francis |
2014-08-29 | target-arm: Add arm_ccnt_enabled function | Alistair Francis |
2014-08-29 | target-arm: Implement PMCCNTR_EL0 and related registers | Alistair Francis |
2014-08-29 | arm: Implement PMCCNTR 32b read-modify-write | Peter Crosthwaite |
2014-08-29 | target-arm: Make the ARM PMCCNTR register 64-bit | Alistair Francis |
2014-08-19 | target-arm: Implement MDSCR_EL1 as having state | Peter Maydell |
2014-08-19 | target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 | Peter Maydell |
2014-08-19 | target-arm: Adjust debug ID registers per-CPU | Peter Maydell |
2014-08-19 | target-arm: Provide both 32 and 64 bit versions of debug registers | Peter Maydell |
2014-08-19 | target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 | Peter Maydell |
2014-08-19 | target-arm: Collect up the debug cp register definitions | Peter Maydell |
2014-08-04 | target-arm: A64: fix TLB flush instructions | Alex Bennée |
2014-08-04 | target-arm: don't hardcode mask values in arm_cpu_handle_mmu_fault | Alex Bennée |
2014-08-04 | target-arm: Fix bit test in sp_el0_access | Stefan Weil |
2014-08-04 | target-arm: Add FAR_EL2 and 3 | Edgar E. Iglesias |
2014-08-04 | target-arm: Add ESR_EL2 and 3 | Edgar E. Iglesias |
2014-08-04 | target-arm: Make far_el1 an array | Edgar E. Iglesias |
2014-06-24 | Fix new typos (found by codespell) | Stefan Weil |
2014-06-19 | target-arm: Add ULL suffix to calculation of page size | Peter Maydell |
2014-06-19 | target-arm: implement PD0/PD1 bits for TTBCR | Fabian Aggeler |
2014-06-09 | target-arm: Fix errors in writes to generic timer control registers | Peter Maydell |
2014-06-09 | target-arm: A32/T32: Mask CRC value in calling code, not helper | Peter Maydell |
2014-06-09 | target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables | Ian Campbell |
2014-06-09 | target-arm: Prepare cpreg writefns/readfns for EL3/SecExt | Fabian Aggeler |
2014-06-05 | softmmu: introduce cpu_ldst.h | Paolo Bonzini |
2014-06-05 | target-arm: move arm_*_code to a separate file | Paolo Bonzini |
2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson |
2014-05-27 | target-arm: A64: Register VBAR_EL3 | Edgar E. Iglesias |
2014-05-27 | target-arm: A64: Register VBAR_EL2 | Edgar E. Iglesias |
2014-05-27 | target-arm: Make vbar_write writeback to any CPREG | Edgar E. Iglesias |
2014-05-27 | target-arm: Register EL3 versions of ELR and SPSR | Edgar E. Iglesias |
2014-05-27 | target-arm: Register EL2 versions of ELR and SPSR | Edgar E. Iglesias |
2014-05-27 | target-arm: Add SPSR entries for EL2/HYP and EL3/MON | Edgar E. Iglesias |
2014-05-27 | target-arm: c12_vbar -> vbar_el[] | Edgar E. Iglesias |
2014-05-27 | target-arm: Make esr_el1 an array | Edgar E. Iglesias |
2014-05-27 | target-arm: Make elr_el1 an array | Edgar E. Iglesias |
2014-05-27 | target-arm: implement CPACR register logic for ARMv7 | Fabian Aggeler |