Age | Commit message (Expand) | Author |
2016-03-16 | target-arm: Fix translation level on early translation faults | Sergey Sorokin |
2016-03-04 | target-arm: implement SCTLR.EE | Peter Crosthwaite |
2016-03-04 | target-arm: implement SCTLR.B, drop bswap_code | Paolo Bonzini |
2016-03-04 | target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode | Peter Maydell |
2016-02-26 | target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF | Peter Maydell |
2016-02-26 | target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW | Edgar E. Iglesias |
2016-02-26 | target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps | Peter Maydell |
2016-02-26 | target-arm: Fix handling of SDCR for 32-bit code | Peter Maydell |
2016-02-26 | target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 | Peter Maydell |
2016-02-26 | target-arm: Make mode switches from Hyp via CPS and MRS illegal | Peter Maydell |
2016-02-26 | target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL | Peter Maydell |
2016-02-26 | target-arm: Forbid mode switch to Mon from Secure EL1 | Peter Maydell |
2016-02-26 | target-arm: Add Hyp mode checks to bad_mode_switch() | Peter Maydell |
2016-02-26 | target-arm: Add comment about not implementing NSACR.RFR | Peter Maydell |
2016-02-26 | target-arm: In cpsr_write() ignore mode switches from User mode | Peter Maydell |
2016-02-26 | target-arm: Raw CPSR writes should skip checks and bank switching | Peter Maydell |
2016-02-26 | target-arm: Add write_type argument to cpsr_write() | Peter Maydell |
2016-02-18 | target-arm: Add PMUSERENR_EL0 register | Alistair Francis |
2016-02-18 | target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers | Alistair Francis |
2016-02-18 | target-arm: Add the pmceid0 and pmceid1 registers | Alistair Francis |
2016-02-18 | target-arm: Move bank_number() into internals.h | Peter Maydell |
2016-02-18 | target-arm: Move get/set_r13_banked() to op_helper.c | Peter Maydell |
2016-02-18 | target-arm: Report correct syndrome for FPEXC32_EL2 traps | Peter Maydell |
2016-02-18 | target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA traps | Peter Maydell |
2016-02-18 | target-arm: Implement MDCR_EL2.TDRA traps | Peter Maydell |
2016-02-18 | target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps | Peter Maydell |
2016-02-18 | target-arm: correct CNTFRQ access rights | Peter Maydell |
2016-02-11 | target-arm: Implement NSACR trapping behaviour | Peter Maydell |
2016-02-11 | target-arm: Add isread parameter to CPAccessFns | Peter Maydell |
2016-02-11 | target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR | Peter Maydell |
2016-02-11 | target-arm: Implement MDCR_EL3 and SDCR | Peter Maydell |
2016-02-03 | target-arm: Implement the S2 MMU inputsize > pamax check | Edgar E. Iglesias |
2016-02-03 | target-arm: Rename check_s2_startlevel to check_s2_mmu_setup | Edgar E. Iglesias |
2016-02-03 | target-arm: Apply S2 MMU startlevel table size check to AArch64 | Edgar E. Iglesias |
2016-02-03 | target-arm: Make various system registers visible to EL3 | Peter Maydell |
2016-01-21 | target-arm: Implement FPEXC32_EL2 system register | Peter Maydell |
2016-01-21 | target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target | Peter Maydell |
2016-01-21 | target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() | Peter Maydell |
2016-01-21 | target-arm: Use a single entry point for AArch64 and AArch32 exceptions | Peter Maydell |
2016-01-21 | target-arm: Move aarch64_cpu_do_interrupt() to helper.c | Peter Maydell |
2016-01-21 | target-arm: Support multiple address spaces in page table walks | Peter Maydell |
2016-01-21 | target-arm: Implement cpu_get_phys_page_attrs_debug | Peter Maydell |
2016-01-18 | target-arm: Clean up includes | Peter Maydell |
2016-01-15 | target-arm: Use the right MMU index in arm_regime_using_lpae_format | Alvise Rigo |
2015-12-17 | target-arm: raise exception on misaligned LDREX operands | Andrew Baumann |
2015-11-24 | target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8 | Peter Maydell |
2015-11-03 | target-arm: Add and use symbolic names for register banks | Soren Brinkmann |
2015-10-27 | target-arm: Add support for S1 + S2 MMU translations | Edgar E. Iglesias |
2015-10-27 | target-arm: Add S2 translation to 32bit S1 PTWs | Edgar E. Iglesias |
2015-10-27 | target-arm: Add S2 translation to 64bit S1 PTWs | Edgar E. Iglesias |