Age | Commit message (Expand) | Author |
2014-12-22 | target-arm: Merge EL3 CP15 register lists | Greg Bellows |
2014-12-11 | target-arm: make MAIR0/1 banked | Greg Bellows |
2014-12-11 | target-arm: make c13 cp regs banked (FCSEIDR, ...) | Fabian Aggeler |
2014-12-11 | target-arm: make VBAR banked | Greg Bellows |
2014-12-11 | target-arm: make PAR banked | Fabian Aggeler |
2014-12-11 | target-arm: make IFAR/DFAR banked | Fabian Aggeler |
2014-12-11 | target-arm: make DFSR banked | Fabian Aggeler |
2014-12-11 | target-arm: make IFSR banked | Fabian Aggeler |
2014-12-11 | target-arm: make DACR banked | Fabian Aggeler |
2014-12-11 | target-arm: make TTBCR banked | Fabian Aggeler |
2014-12-11 | target-arm: make TTBR0/1 banked | Fabian Aggeler |
2014-12-11 | target-arm: make CSSELR banked | Fabian Aggeler |
2014-12-11 | target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI | Fabian Aggeler |
2014-12-11 | target-arm: add SCTLR_EL3 and make SCTLR banked | Fabian Aggeler |
2014-12-11 | target-arm: add MVBAR support | Fabian Aggeler |
2014-12-11 | target-arm: add SDER definition | Greg Bellows |
2014-12-11 | target-arm: add NSACR register | Fabian Aggeler |
2014-12-11 | target-arm: implement IRQ/FIQ routing to Monitor mode | Fabian Aggeler |
2014-12-11 | target-arm: move AArch32 SCR into security reglist | Fabian Aggeler |
2014-12-11 | target-arm: insert AArch32 cpregs twice into hashtable | Fabian Aggeler |
2014-12-11 | target-arm: add secure state bit to CPREG hash | Peter Maydell |
2014-12-11 | target-arm: add async excp target_el function | Greg Bellows |
2014-11-17 | target-arm: handle address translations that start at level 3 | Peter Maydell |
2014-10-24 | target-arm: A32: Emulate the SMC instruction | Fabian Aggeler |
2014-10-24 | target-arm: rename arm_current_pl to arm_current_el | Greg Bellows |
2014-10-24 | target-arm: reject switching to monitor mode | Sergey Fedorov |
2014-10-24 | target-arm: Correct sense of the DCZID DZP bit | Peter Maydell |
2014-10-24 | target-arm: add emulation of PSCI calls for system emulation | Rob Herring |
2014-10-24 | target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes | Rob Herring |
2014-09-29 | target-arm: Add support for VIRQ and VFIQ | Edgar E. Iglesias |
2014-09-29 | target-arm: Add IRQ and FIQ routing to EL2 and 3 | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the SMC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: Add a Hypervisor Trap exception type | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Emulate the HVC insn | Edgar E. Iglesias |
2014-09-29 | target-arm: A64: Refactor aarch64_cpu_do_interrupt | Edgar E. Iglesias |
2014-09-29 | target-arm: Add SCR_EL3 | Edgar E. Iglesias |
2014-09-29 | target-arm: Add HCR_EL2 | Edgar E. Iglesias |
2014-09-29 | target-arm: Don't handle c15_cpar changes via tb_flush() | Peter Maydell |
2014-09-29 | target-arm: Implement setting guest breakpoints | Peter Maydell |
2014-09-12 | target-arm: Make *IS TLB maintenance ops affect all CPUs | Peter Maydell |
2014-09-12 | target-arm: Push legacy wildcard TLB ops back into v6 | Peter Maydell |
2014-09-12 | target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 | Peter Maydell |
2014-09-12 | target-arm: Remove comment about MDSCR_EL1 being dummy implementation | Peter Maydell |
2014-09-12 | target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 | Peter Maydell |
2014-09-12 | target-arm: Implement handling of fired watchpoints | Peter Maydell |
2014-09-12 | target-arm: Move extended_addresses_enabled() to internals.h | Peter Maydell |
2014-09-12 | target-arm: Implement setting of watchpoints | Peter Maydell |
2014-08-29 | target-arm: Implement pmccfiltr_write function | Alistair Francis |
2014-08-29 | target-arm: Remove old code and replace with new functions | Alistair Francis |
2014-08-29 | target-arm: Implement pmccntr_sync function | Alistair Francis |