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path: root/target-arm/helper.c
AgeCommit message (Expand)Author
2015-02-13target-arm: Add 32/64-bit register syncGreg Bellows
2015-02-05target-arm: fix for exponent comparison in recpe_f64Ildar Isaev
2015-02-05target-arm: Fix brace style in reindented codePeter Maydell
2015-02-05target-arm: Reindent ancient page-table-walk codePeter Maydell
2015-02-05target-arm: Use mmu_idx in get_phys_addr()Peter Maydell
2015-02-05target-arm: Pass mmu_idx to get_phys_addr()Peter Maydell
2015-02-05target-arm: Split AArch64 cases out of ats_write()Peter Maydell
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell
2015-02-05target-arm: Add checks that cpreg raw accesses are handledPeter Maydell
2015-02-05target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell
2015-02-05target-arm: Add missing SP_ELx register definitionGreg Bellows
2015-02-05target-arm: Add extended RVBAR supportGreg Bellows
2015-02-05target-arm: Fix RVBAR_EL1 register encodingGreg Bellows
2015-01-15target-arm: Fix typo in comment (seperately -> separately)Stefan Weil
2014-12-22target-arm: Merge EL3 CP15 register listsGreg Bellows
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler
2014-12-11target-arm: make VBAR bankedGreg Bellows
2014-12-11target-arm: make PAR bankedFabian Aggeler
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler
2014-12-11target-arm: make DFSR bankedFabian Aggeler
2014-12-11target-arm: make IFSR bankedFabian Aggeler
2014-12-11target-arm: make DACR bankedFabian Aggeler
2014-12-11target-arm: make TTBCR bankedFabian Aggeler
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler
2014-12-11target-arm: make CSSELR bankedFabian Aggeler
2014-12-11target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler
2014-12-11target-arm: add MVBAR supportFabian Aggeler
2014-12-11target-arm: add SDER definitionGreg Bellows
2014-12-11target-arm: add NSACR registerFabian Aggeler
2014-12-11target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler
2014-12-11target-arm: move AArch32 SCR into security reglistFabian Aggeler
2014-12-11target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell
2014-12-11target-arm: add async excp target_el functionGreg Bellows
2014-11-17target-arm: handle address translations that start at level 3Peter Maydell
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias
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