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2012-04-27target-arm: Change cpu_arm_init() return type to ARMCPUAndreas Färber
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to obtain an ARMCPU through arm_env_get_cpu() in machine init code. This requires to adjust the inclusion site of cpu-qom.h and in turn, forward-looking, to homogenize its include order. cpu_init() must still return a CPUARMState for backwards and cross-target compatibility, so adjust the cpu_init macro. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21target-arm: Move reset handling to arm_cpu_resetPeter Maydell
Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Drop cpu_reset_model_id()Peter Maydell
cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move cache ID register setup to cpu specific init fnsPeter Maydell
Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_resetPeter Maydell
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move feature register setup to per-CPU init fnsPeter Maydell
Move feature register value setup to per-CPU init functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move iWMMXT wCID reset to cpu_state_resetPeter Maydell
Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Drop JTAG_ID documentationPeter Maydell
None of the machines in QEMU offer a JTAG debug interface, so this info was unused. Further, the PXA250 ID contradicts the February 2002 Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21target-arm: Move SCTLR reset value setup to per cpu init fnsPeter Maydell
Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move CTR setup to per cpu init fnsPeter Maydell
Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move MVFR* setup to per cpu init fnsPeter Maydell
Move the MVFR* VFP feature register values to ARMCPU, so they are set up by the implementation-specific instance init functions rather than in cpu_reset_model_id(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move FPSID config to cpu init fnsPeter Maydell
Move the reset FPSID to the ARMCPU struct, and set it in the per-implementation instance init function. At reset we then just copy the reset value into the CPUARMState field. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Move feature bit settings to CPU init fnsPeter Maydell
Move the setting of the feature bits from cpu_reset_model_id() to each CPU's instance init function. This requires us to move the features field in CPUARMState so that it is not cleared on reset. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21target-arm: Add QOM subclasses for each ARM cpu implementationPeter Maydell
Register subclasses for each ARM CPU implementation. Let arm_cpu_list() enumerate CPU subclasses in alphabetical order, except for special value "any". Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the CPUID (aka MIDR, Main ID Register) value in the class. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-06Userspace ARM BE8 supportPaul Brook
Add support for ARM BE8 userspace binaries. i.e. big-endian data and little-endian code. In principle LE8 mode is also possible, but AFAIK has never actually been implemented/used. System emulation doesn't have any useable big-endian board models, but should in principle work once you fix that. Dynamic endianness switching requires messing with data accesses, preferably with TCG cooperation, and is orthogonal to BE8 support. Signed-off-by: Paul Brook <paul@codesourcery.com> [PMM: various changes, mostly as per my suggestions in code review: * rebase * use EF_ defines rather than hardcoded constants * make bswap_code a bool for future VMSTATE macro compatibility * update comment in cpu.h about TB flags bit field usage * factor out load-code-and-swap into arm_ld*_code functions and get_user_code* macros * fix stray trailing space at end of line * added braces in disas.c to satisfy checkpatch ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
2012-03-30ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.Andrew Towers
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu does not support ARM1156 at this time.) MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores. Reference: ARM DDI 0211H, 0290G, 0301H, 0360E. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html Without this change, the linux kernel will not boot with VFP support enabled under ARM1176 system emulation, due to the unconditional use of MVFR1 at the end of vfp_init() in arch/arm/vfp/vfpmodule.c: VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5 Internal error: Oops - undefined instruction: 0 [#1] Signed-off-by: Andrew Towers <atowers@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-29target-arm: Minimalistic CPU QOM'ificationAndreas Färber
Introduce only one non-abstract type TYPE_ARM_CPU and do not touch cp15 registers to not interfere with Peter's ongoing remodelling. Embed CPUARMState as first (additional) field of ARMCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-29target-arm: Drop cpu_arm_close()Andreas Färber
It's unused, so no need to QOM'ify it later. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-15target-arm: Clear IT bits when taking exceptions in v7MPeter Maydell
When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-15target-arm: Fix typo in ARM946 cp15 c5 handlingPeter Maydell
Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling (instruction access permission bits) that meant it would return the data access permission bits by mistake. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-14target-arm: Don't overuse CPUStateAndreas Färber
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-03-14Rename cpu_reset() to cpu_state_reset()Andreas Färber
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-02-28target-arm: Clean includesStefan Weil
Remove some include statements which are not needed. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-17target-arm/helper.c: tb_flush() on CPU resetPeter Maydell
Since target-arm has some CPUState fields for which we take the approach of baking assumptions about them into translated code and then calling tb_flush() when the fields change, we must also tb_flush on CPU reset, because reset is a change of those fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-02-17target-arm/helper.c: Correct FPSID value for Cortex-A9Peter Maydell
The correct FPSID for the Cortex-A9 (according to the TRM) is 0x41033090 for the r0p0 that we claim to model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2012-01-25Add Cortex-A15 CPU definitionPeter Maydell
Add a definition of a Cortex-A15 CPU. Note that for the moment we do not implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc) This CPU model is sufficient to boot a Linux kernel which has been compiled for an A15 without LPAE enabled. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25Add dummy implementation of generic timer cp15 registersPeter Maydell
Add a dummy implementation of the cp15 registers for the generic timer (found in the Cortex-A15), just sufficient for Linux to decide that it can't use it. This requires at least CNTP_CTL and CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25arm: store the config_base_register during cpu_resetMark Langsdorf
Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25target-arm/helper.c: Don't assume softfloat int32 is 32 bits onlyPeter Maydell
In the helper routines for VCVT float-to-int conversions, add an explicit cast rather than relying on the softfloat int32 type being exactly 32 bits wide (which it is not guaranteed to be). Without this, if the softfloat type was 64 bits wide we would get zero-extension of the 32 bit value from the ARM register rather than sign-extension, since TCG i32 values are passed as uint32_t. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-25target-arm: Fix implementation of TLB invalidate operationsPeter Maydell
Fix some bugs in the implementation of the TLB invalidate operations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since tlb_flush() currently ignores that argument, but is semantically incorrect * 'invalidate by address for all ASIDs' was implemented as flushing the whole TLB, which invalidates much more than strictly necessary. Use tlb_flush_page() instead. We also annotate the ops with the ARM ARM official acronyms. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-13arm: Add dummy support for co-processor 15's secure config registerRob Herring
Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05arm: add dummy A9-specific cp15 registersMark Langsdorf
Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05target-arm: Ignore attempts to set invalid modes in CPSRPeter Maydell
Ignore attempts to set the CPSR mode field to an invalid value. This is UNPREDICTABLE, but we should not cpu_abort() for things a malicious guest (or a confused user on the gdbstub interface) can provoke. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-01-05target-arm: Don't use cpu_single_env in bank_number()Peter Maydell
Avoid using cpu_single_env in bank_number() -- if we were called via the gdb stub reading or writing the CPSR then it is NULL and we will segfault if we take the cpu_abort(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer VFPv3 feature from VFPv4Andreas Färber
VFP4 => VFP3 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer VFP feature from VFPv3Andreas Färber
VFP3 => VFP Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer Thumb division feature from M profileAndreas Färber
M => THUMB_DIV Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer Thumb2 feature from ARMv7Andreas Färber
V7 => THUMB2 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer AUXCR feature from ARMv6Andreas Färber
V6 && !M => AUXCR Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv6(K) feature from ARMv7Andreas Färber
V7 && M => V6 V7 && !M => V6K Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv6 feature from v6KAndreas Färber
V6K => V6 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv5 feature from ARMv6Andreas Färber
V6 => V5 Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13target-arm: Infer ARMv4T feature from ARMv5Andreas Färber
V5 => V4T Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-13arm: Fix CP15 FSR (C5) domain settingJean-Christophe DUBOIS
Return the correct value in the domain field in the cp15 DFSR (C5) -- bug noticed during Xvisor development. Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net> [Peter Maydell: reworded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-12-05target-arm/helper.c: Don't allocate TCG resources unless TCG enabledPeter Maydell
Don't call arm_translate_init() (which allocates TCG resources) unless TCG is enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-10-20target-arm: Fix use of free() in cpu_arm_close()Andreas Färber
env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free(). Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Implement VFPv4 fused multiply-accumulate insnsPeter Maydell
Implement the fused multiply-accumulate instructions (VFMA, VFMS, VFNMA, VFNMS) which are new in VFPv4. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Add ARM UDIV/SDIV supportPeter Maydell
Add support for UDIV and SDIV in ARM mode. This is a new optional feature for A profile cores (Thumb mode has had UDIV and SDIV for M profile cores for some time). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIVPeter Maydell
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to make room for a new feature switch enabling DIV in the ARM encoding. (Cores may implement either (a) no divide insns (b) divide insns in Thumb encodings only (c) divide insns in both ARM and Thumb encodings.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2011-10-19rsqrte_f32: No need to copy sign bit.Christophe LYON
Indeed, the result is known to be always positive. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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