Age | Commit message (Expand) | Author |
2014-06-09 | target-arm: A64: Implement CRC instructions | Peter Maydell |
2014-06-09 | target-arm: add support for v8 VMULL.P64 instruction | Peter Maydell |
2014-05-28 | tcg: Invert the inclusion of helper.h | Richard Henderson |
2014-05-27 | target-arm: A64: Introduce aarch64_banked_spsr_index() | Edgar E. Iglesias |
2014-05-27 | target-arm: c12_vbar -> vbar_el[] | Edgar E. Iglesias |
2014-05-27 | target-arm: Make esr_el1 an array | Edgar E. Iglesias |
2014-05-27 | target-arm: Make elr_el1 an array | Edgar E. Iglesias |
2014-04-17 | target-arm: Implement AArch64 EL1 exception handling | Rob Herring |
2014-03-17 | target-arm: A64: Implement FCVTXN | Peter Maydell |
2014-03-17 | target-arm: A64: Add FRECPX (reciprocal exponent) | Alex Bennée |
2014-03-17 | target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP | Peter Maydell |
2014-03-17 | target-arm: A64: Add remaining CLS/Z vector ops | Alex Bennée |
2014-03-17 | target-arm: A64: Implement PMULL instruction | Peter Maydell |
2014-02-20 | target-arm: A64: Implement remaining 3-same instructions | Peter Maydell |
2014-02-20 | target-arm: A64: Implement SIMD FP compare and set insns | Alex Bennée |
2014-02-20 | target-arm: A64: Implement plain vector SIMD indexed element insns | Peter Maydell |
2014-01-31 | target-arm: A64: Add SIMD TBL/TBLX | Michael Matz |
2014-01-08 | target-arm: A64: Add support for floating point compare | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 1-src CLS insn | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 1-src RBIT insn | Alexander Graf |
2013-12-17 | target-arm: A64: add support for 1-src data processing and CLZ | Claudio Fontana |
2013-12-17 | target-arm: A64: add support for 2-src data processing and DIV | Alexander Graf |
2013-12-17 | target-arm: A64: add stubs for a64 specific helpers | Alexander Graf |