Age | Commit message (Expand) | Author |
2014-08-29 | target-arm: Implement pmccntr_sync function | Alistair Francis |
2014-08-29 | target-arm: Implement PMCCNTR_EL0 and related registers | Alistair Francis |
2014-08-29 | target-arm: Make the ARM PMCCNTR register 64-bit | Alistair Francis |
2014-08-29 | target-arm: Fix regression that disabled VFP for ARMv5 CPUs | Peter Maydell |
2014-08-19 | target-arm: Implement ARMv8 single-stepping for AArch32 code | Peter Maydell |
2014-08-19 | target-arm: Implement ARMv8 single-step handling for A64 code | Peter Maydell |
2014-08-19 | target-arm: Set PSTATE.SS correctly on exception return from AArch64 | Peter Maydell |
2014-08-19 | target-arm: Don't allow AArch32 to access RES0 CPSR bits | Peter Maydell |
2014-08-04 | target-arm: Add FAR_EL2 and 3 | Edgar E. Iglesias |
2014-08-04 | target-arm: Add ESR_EL2 and 3 | Edgar E. Iglesias |
2014-08-04 | target-arm: Make far_el1 an array | Edgar E. Iglesias |
2014-06-19 | target-arm: implement PD0/PD1 bits for TTBCR | Fabian Aggeler |
2014-06-09 | target-arm: add support for v8 VMULL.P64 instruction | Peter Maydell |
2014-06-09 | target-arm: add support for v8 SHA1 and SHA256 instructions | Ard Biesheuvel |
2014-06-05 | target-arm: move arm_*_code to a separate file | Paolo Bonzini |
2014-05-27 | target-arm: A64: Register VBAR_EL3 | Edgar E. Iglesias |
2014-05-27 | target-arm: A64: Register VBAR_EL2 | Edgar E. Iglesias |
2014-05-27 | target-arm: Add a feature flag for EL3 | Edgar E. Iglesias |
2014-05-27 | target-arm: Add a feature flag for EL2 | Edgar E. Iglesias |
2014-05-27 | target-arm: Add SPSR entries for EL2/HYP and EL3/MON | Edgar E. Iglesias |
2014-05-27 | target-arm: A64: Add ELR entries for EL2 and 3 | Edgar E. Iglesias |
2014-05-27 | target-arm: A64: Add SP entries for EL2 and 3 | Edgar E. Iglesias |
2014-05-27 | target-arm: c12_vbar -> vbar_el[] | Edgar E. Iglesias |
2014-05-27 | target-arm: Make esr_el1 an array | Edgar E. Iglesias |
2014-05-27 | target-arm: Make elr_el1 an array | Edgar E. Iglesias |
2014-05-27 | target-arm: Use a 1:1 mapping between EL and MMU index | Edgar E. Iglesias |
2014-04-17 | target-arm: Implement CBAR for Cortex-A57 | Peter Maydell |
2014-04-17 | target-arm: Implement AArch64 address translation operations | Peter Maydell |
2014-04-17 | target-arm: Implement AArch64 view of CONTEXTIDR | Peter Maydell |
2014-04-17 | target-arm: Implement ARMv8 MVFR registers | Peter Maydell |
2014-04-17 | target-arm: Implement AArch64 SPSR_EL1 | Peter Maydell |
2014-04-17 | target-arm: Implement SP_EL0, SP_EL1 | Peter Maydell |
2014-04-17 | target-arm: Add AArch64 ELR_EL1 register. | Peter Maydell |
2014-04-17 | target-arm: Implement AArch64 views of fault status and data registers | Rob Herring |
2014-04-17 | target-arm: Use dedicated CPU state fields for ARM946 access bit registers | Peter Maydell |
2014-04-17 | target-arm: A64: Implement DC ZVA | Peter Maydell |
2014-04-17 | target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1 | Peter Maydell |
2014-04-17 | target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set | Peter Maydell |
2014-04-17 | target-arm: Define exception record for AArch64 exceptions | Peter Maydell |
2014-04-17 | target-arm: Implement AArch64 DAIF system register | Peter Maydell |
2014-04-17 | target-arm: Split out private-to-target functions into internals.h | Peter Maydell |
2014-03-13 | cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook | Andreas Färber |
2014-03-13 | cpu: Turn cpu_has_work() into a CPUClass hook | Andreas Färber |
2014-03-10 | target-arm: Implements the ARM PMCCNTR register | Alistair Francis |
2014-02-26 | target-arm: Add support for AArch32 ARMv8 CRC32 instructions | Will Newton |
2014-02-26 | target-arm: Add utility function for checking AA32/64 state of an EL | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 view of CPACR | Peter Maydell |
2014-02-26 | target-arm: Store AIF bits in env->pstate for AArch32 | Peter Maydell |
2014-02-26 | target-arm: Get MMU index information correct for A64 code | Peter Maydell |
2014-02-26 | target-arm: Implement AArch64 dummy breakpoint and watchpoint registers | Peter Maydell |