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QEMU is a generic and open source machine & userspace emulator and virtualizer
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target-arm
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cpu.h
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Author
2015-02-05
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW
Peter Maydell
2015-01-20
exec.c: Drop TARGET_HAS_ICE define and checks
Peter Maydell
2014-12-11
target-arm: make MAIR0/1 banked
Greg Bellows
2014-12-11
target-arm: make c13 cp regs banked (FCSEIDR, ...)
Fabian Aggeler
2014-12-11
target-arm: make VBAR banked
Greg Bellows
2014-12-11
target-arm: make PAR banked
Fabian Aggeler
2014-12-11
target-arm: make IFAR/DFAR banked
Fabian Aggeler
2014-12-11
target-arm: make DFSR banked
Fabian Aggeler
2014-12-11
target-arm: make IFSR banked
Fabian Aggeler
2014-12-11
target-arm: make DACR banked
Fabian Aggeler
2014-12-11
target-arm: make TTBCR banked
Fabian Aggeler
2014-12-11
target-arm: make TTBR0/1 banked
Fabian Aggeler
2014-12-11
target-arm: make CSSELR banked
Fabian Aggeler
2014-12-11
target-arm: add SCTLR_EL3 and make SCTLR banked
Fabian Aggeler
2014-12-11
target-arm: add MVBAR support
Fabian Aggeler
2014-12-11
target-arm: add SDER definition
Greg Bellows
2014-12-11
target-arm: add NSACR register
Fabian Aggeler
2014-12-11
target-arm: add secure state bit to CPREG hash
Peter Maydell
2014-12-11
target-arm: add CPREG secure state support
Fabian Aggeler
2014-12-11
target-arm: add non-secure Translation Block flag
Sergey Fedorov
2014-12-11
target-arm: add banked register accessors
Fabian Aggeler
2014-12-11
target-arm: extend async excp masking
Greg Bellows
2014-11-04
target-arm: Correct condition for taking VIRQ and VFIQ
Peter Maydell
2014-11-04
target-arm: Separate out M profile cpu_exec_interrupt handling
Peter Maydell
2014-10-24
target-arm: make arm_current_el() return EL3
Fabian Aggeler
2014-10-24
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
2014-10-24
target-arm: add arm_is_secure() function
Fabian Aggeler
2014-10-24
target-arm: increase arrays of registers R13 & R14
Fabian Aggeler
2014-10-24
target-arm: add emulation of PSCI calls for system emulation
Rob Herring
2014-09-29
target-arm: Add support for VIRQ and VFIQ
Edgar E. Iglesias
2014-09-29
target-arm: Add IRQ and FIQ routing to EL2 and 3
Edgar E. Iglesias
2014-09-29
target-arm: A64: Emulate the SMC insn
Edgar E. Iglesias
2014-09-29
target-arm: Add a Hypervisor Trap exception type
Edgar E. Iglesias
2014-09-29
target-arm: A64: Emulate the HVC insn
Edgar E. Iglesias
2014-09-29
target-arm: Don't take interrupts targeting lower ELs
Edgar E. Iglesias
2014-09-29
target-arm: Break out exception masking to a separate func
Edgar E. Iglesias
2014-09-29
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Edgar E. Iglesias
2014-09-29
target-arm: Add SCR_EL3
Edgar E. Iglesias
2014-09-29
target-arm: Add HCR_EL2
Edgar E. Iglesias
2014-09-29
target-arm: Don't handle c15_cpar changes via tb_flush()
Peter Maydell
2014-09-29
target-arm: Implement setting guest breakpoints
Peter Maydell
2014-09-12
target-arm: Implement setting of watchpoints
Peter Maydell
2014-08-29
target-arm: Implement pmccntr_sync function
Alistair Francis
2014-08-29
target-arm: Implement PMCCNTR_EL0 and related registers
Alistair Francis
2014-08-29
target-arm: Make the ARM PMCCNTR register 64-bit
Alistair Francis
2014-08-29
target-arm: Fix regression that disabled VFP for ARMv5 CPUs
Peter Maydell
2014-08-19
target-arm: Implement ARMv8 single-stepping for AArch32 code
Peter Maydell
2014-08-19
target-arm: Implement ARMv8 single-step handling for A64 code
Peter Maydell
2014-08-19
target-arm: Set PSTATE.SS correctly on exception return from AArch64
Peter Maydell
2014-08-19
target-arm: Don't allow AArch32 to access RES0 CPSR bits
Peter Maydell
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