aboutsummaryrefslogtreecommitdiff
path: root/target-arm/cpu.h
AgeCommit message (Expand)Author
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler
2014-12-11target-arm: make VBAR bankedGreg Bellows
2014-12-11target-arm: make PAR bankedFabian Aggeler
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler
2014-12-11target-arm: make DFSR bankedFabian Aggeler
2014-12-11target-arm: make IFSR bankedFabian Aggeler
2014-12-11target-arm: make DACR bankedFabian Aggeler
2014-12-11target-arm: make TTBCR bankedFabian Aggeler
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler
2014-12-11target-arm: make CSSELR bankedFabian Aggeler
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler
2014-12-11target-arm: add MVBAR supportFabian Aggeler
2014-12-11target-arm: add SDER definitionGreg Bellows
2014-12-11target-arm: add NSACR registerFabian Aggeler
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell
2014-12-11target-arm: add CPREG secure state supportFabian Aggeler
2014-12-11target-arm: add non-secure Translation Block flagSergey Fedorov
2014-12-11target-arm: add banked register accessorsFabian Aggeler
2014-12-11target-arm: extend async excp maskingGreg Bellows
2014-11-04target-arm: Correct condition for taking VIRQ and VFIQPeter Maydell
2014-11-04target-arm: Separate out M profile cpu_exec_interrupt handlingPeter Maydell
2014-10-24target-arm: make arm_current_el() return EL3Fabian Aggeler
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows
2014-10-24target-arm: add arm_is_secure() functionFabian Aggeler
2014-10-24target-arm: increase arrays of registers R13 & R14Fabian Aggeler
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias
2014-09-29target-arm: Don't take interrupts targeting lower ELsEdgar E. Iglesias
2014-09-29target-arm: Break out exception masking to a separate funcEdgar E. Iglesias
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias
2014-09-29target-arm: Add HCR_EL2Edgar E. Iglesias
2014-09-29target-arm: Don't handle c15_cpar changes via tb_flush()Peter Maydell
2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-16 13:01:04 +0000