Age | Commit message (Expand) | Author |
2015-06-19 | target-arm: Add support for Cortex-R5 | Peter Crosthwaite |
2015-06-19 | target-arm: Add registers for PMSAv7 | Peter Crosthwaite |
2015-06-19 | target-arm/helper.c: define MPUIR register | Peter Crosthwaite |
2015-06-19 | target-arm: Do not reset sysregs marked as ALIAS | Sergey Fedorov |
2015-06-19 | target-arm: Add the Cortex-M4 CPU | Aurelio C. Remonda |
2015-06-15 | arm: Add has-mpu property | Peter Crosthwaite |
2015-06-15 | target-arm: Add the THUMB_DSP feature | Aurelio C. Remonda |
2015-06-15 | target-arm: Use the kernel's idea of MPIDR if we're using KVM | Pavel Fedin |
2015-05-29 | target-arm: Update interrupt handling to use target EL | Greg Bellows |
2015-05-29 | target-arm: Move setting of exception info into tlb_fill | Peter Maydell |
2015-04-26 | target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled | Sergey Fedorov |
2015-04-26 | target-arm: rename c1_coproc to cpacr_el1 | Sergey Fedorov |
2015-02-13 | target-arm: Add CPU property to disable AArch64 | Greg Bellows |
2015-02-05 | target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64 | Pranavkumar Sawargaonkar |
2015-02-05 | target-arm: Change reset to highest available EL | Greg Bellows |
2014-12-22 | target-arm: add cpu feature EL3 to CPUs with Security Extensions | Fabian Aggeler |
2014-12-22 | target-arm: Add ARMCPU secure property | Greg Bellows |
2014-12-22 | target-arm: Add feature unset function | Greg Bellows |
2014-12-11 | target-arm: make IFAR/DFAR banked | Fabian Aggeler |
2014-12-11 | target-arm: add SCTLR_EL3 and make SCTLR banked | Fabian Aggeler |
2014-11-04 | target-arm: Separate out M profile cpu_exec_interrupt handling | Peter Maydell |
2014-10-24 | target-arm: Correct sense of the DCZID DZP bit | Peter Maydell |
2014-10-24 | target-arm: add emulation of PSCI calls for system emulation | Rob Herring |
2014-10-24 | target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes | Rob Herring |
2014-10-24 | target-arm: add powered off cpu state | Rob Herring |
2014-10-06 | gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flag | Peter Maydell |
2014-09-29 | target-arm: Add support for VIRQ and VFIQ | Edgar E. Iglesias |
2014-09-29 | target-arm: Break out exception masking to a separate func | Edgar E. Iglesias |
2014-09-29 | target-arm: Don't handle c15_cpar changes via tb_flush() | Peter Maydell |
2014-09-29 | target-arm: Implement setting guest breakpoints | Peter Maydell |
2014-09-25 | target-arm: Use cpu_exec_interrupt qom hook | Richard Henderson |
2014-09-12 | target-arm: Implement handling of fired watchpoints | Peter Maydell |
2014-09-12 | target-arm: Implement setting of watchpoints | Peter Maydell |
2014-09-12 | target-arm: Fix broken indentation in arm_cpu_reest() | Martin Galvan |
2014-09-12 | target-arm: Fix resetting issues on ARMv7-M CPUs | Martin Galvan |
2014-08-19 | arm: cortex-a9: Fix cache-line size and associativity | Peter Crosthwaite |
2014-08-19 | target-arm: Adjust debug ID registers per-CPU | Peter Maydell |
2014-08-04 | target-arm: Make far_el1 an array | Edgar E. Iglesias |
2014-06-19 | target-arm: Introduce per-CPU field for PSCI version | Pranavkumar Sawargaonkar |
2014-06-09 | target-arm: VFPv4 implies half-precision extension | Peter Maydell |
2014-06-09 | target-arm: Clean up handling of ARMv8 optional feature bits | Peter Maydell |
2014-06-09 | target-arm: Remove unnecessary setting of feature bits | Peter Maydell |
2014-06-09 | target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 | Peter Maydell |
2014-06-09 | target-arm: add support for v8 VMULL.P64 instruction | Peter Maydell |
2014-06-09 | target-arm: add support for v8 SHA1 and SHA256 instructions | Ard Biesheuvel |
2014-05-27 | target-arm: Fix segfault on startup when KVM enabled | Christoffer Dall |
2014-05-13 | kvm: reset state from the CPU's reset method | Paolo Bonzini |
2014-04-17 | target-arm: Make Cortex-A15 CBAR read-only | Peter Maydell |
2014-04-17 | target-arm: Implement CBAR for Cortex-A57 | Peter Maydell |
2014-04-17 | target-arm: Implement RVBAR register | Peter Maydell |