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2008-11-11target-alpha: fix decoding of CVTST /Saurel32
This patch fixes the decoding of CVTST /S which was incorrectly being decoded as CVTTS. This fixes SPEC2000 gcc with 200.i input. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5693 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-alpha: disable single stepping and TB flush by defaultaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5690 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-11target-alpha: fix double TCG variable allocationaurel32
Noticed by Chris Krumme. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5671 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-10target-alpha: fix cmpbge instructionaurel32
The cmpbge instruction should compare all 8 bytes of one 64-bit value with another. However, we were looping with a < 7 condition which was skipping the top byte. So if we were doing a compare where the top byte was important, we could get the wrong result (this notably breaks the strlen() function with certain sized strings). (Vince Weaver) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5667 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-08target-alpha: fix the return value of stl_c/stq_caurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5649 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-07target-alpha: fix locked loads/storesaurel32
Fix reading of cpu_lock in gen_qemu_stql_c, original patch from Laurent Desnogues. A new flag was added to gen_store_mem to allocate local temps instead of temps; this flag should be set when the tcg_gen_qemu_store callback uses brcond before using the temps or else liveness analysis will get rid of the temps. This also adds lock printing in cpu_dump_state which can help debug. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5645 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-06target-alpha: Fix ret instructionaurel32
Hopefully pine doesn't corrupt this patch, I've had problems recently. For an alpha "ret" instruction, of the type ret $26 The return was being ignored. This is because in translate.c register $26 (the return address) was being over-written with the current PC before it could be jumped to. Thus the ret was ignored. This patch just re-orders things so the return address is processed before it is over-written with the current PC. (Vince Weaver) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5638 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-21target-alpha: use the new TCG logical operationsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5502 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-01target-alpha: update STATUSaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5370 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-30target-alpha: convert palcode ops to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-30target-alpha: convert locked load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5359 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29target-alpha: misc fixesaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5355 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29target-alpha: convert FP ops to TCGaurel32
- Convert FP ops to TCG - Fix S format - Implement F and G formats (untested) - Fix MF_FPCR an MT_FPCR - Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT - Fix CPYSN, CPYSE Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-29target-alpha: factorize load/store codeaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5353 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-20Suppress gcc 4.x -Wpointer-sign (included in -Wall) warningsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18target-alpha: switch most load/store ops to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5255 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18target-alpha: convert remaining arith3 functions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18target-alpha: fix one more literal sign issueaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5251 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18target-alpha: instruction decoding simplificationaurel32
Use a litteral value of 0 when rb31 is used. This reduces the tests in the instruction decoding. Also remove almost unused corner cases. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5250 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18target-alpha: convert cmp* instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5249 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18alpha: fix a missing literal sign issueaurel32
Reported by Tristan Gingold git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5248 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-18target-alpha: switch a few helpers to TCGaurel32
Switch a few helpers to TCG and implement RC and RS instructions Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-17target-alpha: convert byte manipulation instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-17alpha: convert cmov and bcond to TCGaurel32
Patch mostly by Tristan Gingold git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5245 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16target-alpha: small optimizationsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5238 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16target-alpha: fix TCG register namesaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5237 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16target-alpha: convert some arith3 instructions to TCGaurel32
Replace gen_arith3 generic macro and dyngen ops by instruction specific optimized TCG code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5236 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-16target-alpha: convert arith2 instructions to TCGaurel32
Replace gen_arith2 generic macro and dyngon ops by instruction specific optimized TCG code. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14alpha: fix helper.haurel32
the content of target-alpha/helper.h is duplicated twice (Tristan Gingold) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5212 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14alpha: fix lit signaurel32
according to the alpha arch reference, the literal field of an operate instruction is unsigned: If bit <12> of the instruction is 1, an 8-bit zero-extended literal constant is formed by bits <20:13> of the instruction. The l teral is interpreted as a positive integer bet ween 0 and 255 and is zero-extended to 64 bits. This patch fixes the mis-interpretation of the literal field. (Tristan Gingold) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5211 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-14Fix warnings that would be caused by gcc flag -Wwrite-stringsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5206 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-05fix alpha cmovxx instructionaurel32
The CMOV instruction is defined by the alpha manual as: CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format Operation: IF TEST(Rav, Condition_based_on_Opcode) THEN Rc ← Rbv The current qemu behavior inverses Ra and Rb. This is fixed by this patch. Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04alpha: add target-alpha/helper.h (missing from commit r5150)aurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5161 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04alpha: convert a few more instructions to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04alpha: directly access ir registersaurel32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-04convert of few alpha insn to TCGaurel32
(based on a patch from Tristan Gingold) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02Fix call_pal() prototype for alpha system emulationaurel32
(Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5131 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Fix warnings that would be generated by gcc -Wstrict-prototypesblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook
Save and restore env->interrupt_request and env->halted. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29Add missing static qualifiers.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-29Add instruction counter.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30Fix typo.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-30Move clone() register setup to target specific code. Handle fork-like clone.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-29Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-28moved halted field to CPU_COMMONbellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25Fix off-by-one unwinding error.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-28Factorize code in translate.caurel32
(Glauber Costa) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-11Remove osdep.c/qemu-img code duplicationaurel32
(Kevin Wolf) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
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