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2023-06-05linux-user/s390x: Fix single-stepping SVCIlya Leoshkevich
Currently single-stepping SVC executes two instructions. The reason is that EXCP_DEBUG for the SVC instruction itself is masked by EXCP_SVC. Fix by re-raising EXCP_DEBUG. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230510230213.330134-2-iii@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-05-18Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into stagingRichard Henderson
Hexagon update # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmRmgQgACgkQewJE+xLe # RCJLtAf8C/0kQRa4mjnbsztXuFyca53UxAv3BSBEDla4ZcMfFBoVJsGB3OP7IPXd # KBQpkLyJAVye9idex5xqdp9nIfoGKDTsc6YtCfGujZ17cDpzLRDpHdUTex8PcZYK # wpfM3hoVJsYRBMsojZ4OaxatjFQ+FWzrIH6FcgH086Q8TH4w9dZLNEJzHC4lOj0s # 7qOuw2tgm+vOVlzsk/fv6/YD/BTeZTON3jgTPvAnvdRLb/482UpM9JkJ8E4rbte3 # Ss5PUK8QTQHU0yamspGy/PfsYxiptM+jIWGd836fAGzwF12Ug27mSc1enndRtQVW # pQTdnOnWuuRzOwEpd7x3xh9upACm4g== # =1CyJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits) Hexagon (linux-user/hexagon): handle breakpoints Hexagon (gdbstub): add HVX support Hexagon (gdbstub): fix p3:0 read and write via stub Hexagon: add core gdbstub xml data for LLDB gdbstub: add test for untimely stop-reply packets gdbstub: only send stop-reply packets when allowed to Remove test_vshuff from hvx_misc tests Hexagon (decode): look for pkts with multiple insns at the same slot Hexagon (iclass): update J4_hintjumpr slot constraints Hexagon: append eflags to unknown cpu model string Hexagon: list available CPUs with `-cpu help` Hexagon (target/hexagon/*.py): raise exception on reg parsing error target/hexagon: fix = vs. == mishap Hexagon (target/hexagon) Additional instructions handled by idef-parser Hexagon (target/hexagon) Move items to DisasContext Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext Hexagon (target/hexagon) Move pred_written to DisasContext Hexagon (target/hexagon) Move new_pred_value to DisasContext Hexagon (target/hexagon) Move new_value to DisasContext Hexagon (target/hexagon) Make special new_value for USR ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-18Hexagon (linux-user/hexagon): handle breakpointsMatheus Tavares Bernardino
This enables LLDB to work with hexagon linux-user mode through the GDB remote protocol. Helped-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <c287a129dcbe7d974d8b7608e8672d34a3c91c04.1683214375.git.quic_mathbern@quicinc.com>
2023-05-18Hexagon: append eflags to unknown cpu model stringMatheus Tavares Bernardino
Running qemu-hexagon with a binary that was compiled for an arch version unknown by qemu can produce a somewhat confusing message: qemu-hexagon: unable to find CPU model 'unknown' Let's give a bit more info by appending the eflags so that the message becomes: qemu-hexagon: unable to find CPU model 'unknown (0x69)' Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <8a8d013cc619b94fd4fb577ae6a8df26cedb972b.1683225804.git.quic_mathbern@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add support for v68/v69/v71/v73Taylor Simpson
Add support for the ELF flags Move target/hexagon/cpu.[ch] to be v73 Change the compiler flag used by "make check-tcg" The decbin instruction is removed in Hexagon v73, so check the version before trying to compile the instruction. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230427224057.3766963-2-tsimpson@quicinc.com>
2023-05-17Merge tag 'linux-user-for-8.1-pull-request' of ↵Richard Henderson
https://github.com/vivier/qemu into staging linux-user pull request 20230512-v4 add open_tree(), move_mount() add /proc/cpuinfo for riscv fixes and cleanup # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmRkiZISHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748FdIP/RC1JaCftkP7ajAstNbZLMLegMxjUYHV # TrdhsMOsm804ZmLgTqqfS3bJ080mIHup0xUnHBckcEtUcwaz54cJ1BAR2WlM3/8A # t3fHMt3PDkh3OPd/3AnmpLE8XRh7yBztirPYfZc6SKqnFzT0TZrwBoQnwprEnZ5r # c0gbrgLZLunZhrWU1BbQmuIufW1qDoQo4PzwnyZeux1fHA1/v/dx3wgSLpv3V4k6 # x0Kj8TvtMUU4/io2RqYF4jKopfhwsh0jnr9rlOmydOExalKq1VbRptJI2UC4KVOY # MZuApF1EaZfrW+v/WSlvmzaZ/zRzP1L0X3Xh0wB4J9Rj3057/elXr6bi+R+rM46p # xGTcti9ahWKP2J4/xrazRw2lfPsLcw/YbqVGG79AX1xLJPCiWq6lamzc/g3ptFnx # F/RRETe65z7apzF/nzU7SDOsMdN5p4/fMb1SysLuAov5OepNVjNVWyiTgqOHB5uC # ye+lOYkkvk+qRdMbls/fIcjDQ3C4AjoBWj4QlgRc0/Qf6ac4TkVjzPa70Y6eyzzS # LEV9D4fXD8EZgYWENNGmbbKPNbtfqc9uR6gXdgkEsKDx/rf5IMf1d6r1C99dhB3A # nbu0JpFKKY2lhD2oGVPDE3UQMW9DXXhZpDApUBsLNiEwfuoXZee+apH+6jc8tbn6 # r+8LFB1mM9os # =NfIV # -----END PGP SIGNATURE----- # gpg: Signature made Wed 17 May 2023 01:00:18 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [undefined] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'linux-user-for-8.1-pull-request' of https://github.com/vivier/qemu: linux-user: fix getgroups/setgroups allocations linux-user: Fix mips fp64 executables loading linux-user: Don't require PROT_READ for mincore linux-user: Add new flag VERIFY_NONE linux-user/main: Use list_cpus() instead of cpu_list() linux-user: Add open_tree() syscall linux-user: Add move_mount() syscall linux-user: report ENOTTY for unknown ioctls linux-user: Emulate /proc/cpuinfo output for riscv Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-17linux-user: fix getgroups/setgroups allocationsMichael Tokarev
linux-user getgroups(), setgroups(), getgroups32() and setgroups32() used alloca() to allocate grouplist arrays, with unchecked gidsetsize coming from the "guest". With NGROUPS_MAX being 65536 (linux, and it is common for an application to allocate NGROUPS_MAX for getgroups()), this means a typical allocation is half the megabyte on the stack. Which just overflows stack, which leads to immediate SIGSEGV in actual system getgroups() implementation. An example of such issue is aptitude, eg https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=811087#72 Cap gidsetsize to NGROUPS_MAX (return EINVAL if it is larger than that), and use heap allocation for grouplist instead of alloca(). While at it, fix coding style and make all 4 implementations identical. Try to not impose random limits - for example, allow gidsetsize to be negative for getgroups() - just do not allocate negative-sized grouplist in this case but still do actual getgroups() call. But do not allow negative gidsetsize for setgroups() since its argument is unsigned. Capping by NGROUPS_MAX seems a bit arbitrary, - we can do more, it is not an error if set size will be NGROUPS_MAX+1. But we should not allow integer overflow for the array being allocated. Maybe it is enough to just call g_try_new() and return ENOMEM if it fails. Maybe there's also no need to convert setgroups() since this one is usually smaller and known beforehand (KERN_NGROUPS_MAX is actually 63, - this is apparently a kernel-imposed limit for runtime group set). The patch fixes aptitude segfault mentioned above. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Message-Id: <20230409105327.1273372-1-mjt@msgid.tls.msk.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: Fix mips fp64 executables loadingDaniil Kovalev
If a program requires fr1, we should set the FR bit of CP0 control status register and add F64 hardware flag. The corresponding `else if` branch statement is copied from the linux kernel sources (see `arch_check_elf` function in linux/arch/mips/kernel/elf.c). Signed-off-by: Daniil Kovalev <dkovalev@compiler-toolchain-for.me> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230404052153.16617-1-dkovalev@compiler-toolchain-for.me> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: Don't require PROT_READ for mincoreThomas Weißschuh
The kernel does not require PROT_READ for addresses passed to mincore. For example the fincore(1) tool from util-linux uses PROT_NONE and currently does not work under qemu-user. Example (with fincore(1) from util-linux 2.38): $ fincore /proc/self/exe RES PAGES SIZE FILE 24K 6 22.1K /proc/self/exe $ qemu-x86_64 /usr/bin/fincore /proc/self/exe fincore: failed to do mincore: /proc/self/exe: Cannot allocate memory With this patch: $ ./build/qemu-x86_64 /usr/bin/fincore /proc/self/exe RES PAGES SIZE FILE 24K 6 22.1K /proc/self/exe Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230422100314.1650-3-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: Add new flag VERIFY_NONEThomas Weißschuh
This can be used to validate that an address range is mapped but without being readable or writable. It will be used by an updated implementation of mincore(). Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230422100314.1650-2-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user/main: Use list_cpus() instead of cpu_list()Thomas Huth
This way we can get rid of the if'deffery and the XXX comment here (it's repeated in the list_cpus() function anyway). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230424122126.236586-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: Add open_tree() syscallThomas Weißschuh
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230424153429.276788-2-thomas@t-8ch.de> [lv: move declaration at the beginning of the block, define syscall] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: Add move_mount() syscallThomas Weißschuh
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> [lv: define syscall] Message-Id: <20230424153429.276788-1-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: report ENOTTY for unknown ioctlsThomas Weißschuh
The correct error number for unknown ioctls is ENOTTY. ENOSYS would mean that the ioctl() syscall itself is not implemented, which is very improbable and unexpected for userspace. ENOTTY means "Inappropriate ioctl for device". This is what the kernel returns on unknown ioctls, what qemu is trying to express and what userspace is prepared to handle. Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230426070659.80649-1-thomas@t-8ch.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-17linux-user: Emulate /proc/cpuinfo output for riscvAfonso Bordado
RISC-V does not expose all extensions via hwcaps, thus some userspace applications may want to query these via /proc/cpuinfo. Currently when querying this file the host's file is shown instead which is slightly confusing. Emulate a basic /proc/cpuinfo file with mmu info and an ISA string. Signed-off-by: Afonso Bordado <afonsobordado@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <167873059442.9885.15152085316575248452-0@git.sr.ht> [lv: removed the test that fails in CI for unknown reason] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-05-11cpu: expose qemu_cpu_list_lock for lock-guard useJamie Iles
Expose qemu_cpu_list_lock globally so that we can use WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths now and in future. Signed-off-by: Jamie Iles <quic_jiles@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427020925.51003-2-quic_jiles@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11disas: Remove target_ulong from the interfaceRichard Henderson
Use uint64_t for the pc, and size_t for the size. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230503072331.1747057-81-richard.henderson@linaro.org>
2023-05-06Merge tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu into ↵Richard Henderson
staging Add LoongArch LSX instructions. # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZFXxGwAKCRBAov/yOSY+ # 39EoA/0Uy2DPz6g7J5+9tcIRk9jLrp36aYQJ9J8zRJd226YFvHSfiBWSIteMFOEX # Z0Jx1bL6N97KK/HA74Nx++x0kVuplEGp1s5cO/odL3gYy8RaJm23p9iaDa0D/UaB # ygLvXtuzN4unDFP5EF/wa9zRkDb7qX2iBBvc8OIal7eT4dDX+g== # =gyVU # -----END PGP SIGNATURE----- # gpg: Signature made Sat 06 May 2023 07:18:03 AM BST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230506' of https://gitlab.com/gaosong/qemu: (45 commits) hw/intc: don't use target_ulong for LoongArch ipi target/loongarch: CPUCFG support LSX target/loongarch: Use {set/get}_gpr replace to cpu_fpr target/loongarch: Implement vldi target/loongarch: Implement vld vst target/loongarch: Implement vilvl vilvh vextrins vshuf target/loongarch: Implement vreplve vpack vpick target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr target/loongarch: Implement vbitsel vset target/loongarch: Implement vfcmp target/loongarch: Implement vseq vsle vslt target/loongarch: Implement LSX fpu fcvt instructions target/loongarch: Implement LSX fpu arith instructions target/loongarch: Implement vfrstp target/loongarch: Implement vbitclr vbitset vbitrev target/loongarch: Implement vpcnt target/loongarch: Implement vclo vclz target/loongarch: Implement vssrlrn vssrarn target/loongarch: Implement vssrln vssran target/loongarch: Implement vsrlrn vsrarn ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-06target/loongarch: Add LSX data type VRegSong Gao
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230504122810.4094787-2-gaosong@loongson.cn>
2023-05-05ppc: spapr: cleanup cr get/set with helpers.Harsh Prateek Bora
The bits in cr reg are grouped into eight 4-bit fields represented by env->crf[8] and the related calculations should be abstracted to keep the calling routines simpler to read. This is a step towards cleaning up the related/calling code for better readability. Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230503093619.2530487-2-harshpb@linux.ibm.com> [danielhb: add 'const' modifier to fix linux-user build] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-05-02linux-user: Add '-one-insn-per-tb' option equivalent to '-singlestep'Peter Maydell
The '-singlestep' option is confusing, because it doesn't actually have anything to do with single-stepping the CPU. What it does do is force TCG emulation to put one guest instruction in each TB, which can be useful in some situations. Create a new command line argument -one-insn-per-tb, so we can document that -singlestep is just a deprecated synonym for it, and eventually perhaps drop it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230417164041.684562-5-peter.maydell@linaro.org
2023-05-02accel/tcg: Use one_insn_per_tb global instead of old singlestep globalPeter Maydell
The only place left that looks at the old 'singlestep' global variable is the TCG curr_cflags() function. Replace the old global with a new 'one_insn_per_tb' which is defined in tcg-all.c and declared in accel/tcg/internal.h. This keeps it restricted to the TCG code, unlike 'singlestep' which was available to every file in the system and defined in multiple different places for softmmu vs linux-user vs bsd-user. While we're making this change, use qatomic_read() and qatomic_set() on the accesses to the new global, because TCG will read it without holding a lock. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230417164041.684562-4-peter.maydell@linaro.org
2023-05-02make one-insn-per-tb an accel optionPeter Maydell
This commit adds 'one-insn-per-tb' as a property on the TCG accelerator object, so you can enable it with -accel tcg,one-insn-per-tb=on It has the same behaviour as the existing '-singlestep' command line option. We use a different name because 'singlestep' has always been a confusing choice, because it doesn't have anything to do with single-stepping the CPU. What it does do is force TCG emulation to put one guest instruction in each TB, which can be useful in some situations (such as analysing debug logs). The existing '-singlestep' commandline options are decoupled from the global 'singlestep' variable and instead now are syntactic sugar for setting the accel property. (These can then go away after a deprecation period.) The global variable remains for the moment as: * what the TCG code looks at to change its behaviour * what HMP and QMP use to query and set the behaviour In the following commits we'll clean those up to not directly look at the global variable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230417164041.684562-2-peter.maydell@linaro.org
2023-04-04Revert "linux-user/arm: Take more care allocating commpage"Richard Henderson
This reverts commit 4f5c67f8df7f26e559509c68c45e652709edd23f. This exposes bugs in target_mmap et al with respect to overflow with the final page of the guest address space. To be fixed in the next development cycle. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-30linux-user/mips: Use P5600 as default CPU to run NaN2008 ELF binariesPhilippe Mathieu-Daudé
Per the release 6.06 revision history: 5.03 August 21, 2013 • ABS2008 and NAN2008 fields of Table 5.7 “FCSR RegisterField Descriptions” were optional in release 3 and could be R/W, but as of release 5 are required, read-only, and preset by hardware. The P5600 core implements the release 5, and has the ABS2008 and NAN2008 bits set in CP1_fcr31. Therefore it is able to run ELF binaries compiled with EF_MIPS_NAN2008, such the CIP United Debian NaN2008 distribution: http://repo.oss.cipunited.com/mipsel-nan2008/README.txt In order to run such compiled binaries, select by default the P5600 core when the ELF 'MIPS_NAN2008' flag is set. Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230327162444.388-1-philmd@linaro.org>
2023-03-30linux-user/sparc: Don't use 16-bit UIDs on SPARC V9Philippe Mathieu-Daudé
The 64-bit SPARC V9 syscall ABI uses 32-bit UIDs. Only enable the 16-bit UID wrappers for 32-bit SPARC (V7 and V8). Possibly missed in commit 992f48a036 ("Support for 32 bit ABI on 64 bit targets (only enabled Sparc64)"). Reported-by: Gregor Riepl <onitake@gmail.com> Tested-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Tested-by: Zach van Rijn <me@zv.io> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1394 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230327131910.78564-1-philmd@linaro.org>
2023-03-28linux-user/arm: Take more care allocating commpageRichard Henderson
User setting of -R reserved_va can lead to an assertion failure in page_set_flags. Sanity check the value of reserved_va and print an error message instead. Do not allocate a commpage at all for m-profile cpus. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-28include/exec: Change reserved_va semantics to last byteRichard Henderson
Change the semantics to be the last byte of the guest va, rather than the following byte. This avoids some overflow conditions. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-28linux-user: Pass last not end to probe_guest_baseRichard Henderson
Pass the address of the last byte of the image, rather than the first address past the last byte. This avoids overflow when the last page of the address space is involved. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-28accel/tcg: Pass last not end to page_reset_target_dataRichard Henderson
Pass the address of the last byte to be changed, rather than the first address past the last byte. This avoids overflow when the last page of the address space is involved. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-28accel/tcg: Pass last not end to page_set_flagsRichard Henderson
Pass the address of the last byte to be changed, rather than the first address past the last byte. This avoids overflow when the last page of the address space is involved. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1528 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-28linux-user: Diagnose misaligned -R sizeRichard Henderson
We have been enforcing host page alignment for the non-R fallback of MAX_RESERVED_VA, but failing to enforce for -R. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-22*: Add missing includes of qemu/plugin.hRichard Henderson
This had been pulled in from hw/core/cpu.h, but that will be removed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230310195252.210956-6-richard.henderson@linaro.org> [AJB: also syscall-trace.h] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230315174331.2959-16-alex.bennee@linaro.org> Reviewed-by: Emilio Cota <cota@braap.org>
2023-03-22*: Add missing includes of qemu/error-report.hRichard Henderson
This had been pulled in via qemu/plugin.h from hw/core/cpu.h, but that will be removed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230310195252.210956-5-richard.henderson@linaro.org> [AJB: add various additional cases shown by CI] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230315174331.2959-15-alex.bennee@linaro.org> Reviewed-by: Emilio Cota <cota@braap.org>
2023-03-12Merge tag 'linux-user-for-8.0-pull-request' of ↵Peter Maydell
https://gitlab.com/laurent_vivier/qemu into staging Pull request linux-user 20230308-v2 Fix gdt on i386/x86_64 Handle traps on sparc Add translation for argument of msync Emulate CLONE_PIDFD flag in clone handle netlink flag NLA_F_NESTED fix sockaddr_in6 endianness Fix brk() to release pages fill out task state in /proc/self/stat add support for xtensa FDPIC Fix unaligned memory access in prlimit64 syscall add target to host netlink conversions fix timerfd read endianness conversion Fix access to /proc/self/exe Add strace for prlimit64() syscall # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmQLqmMSHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748e+cP/3XYMvPbExNi09idDvgzzBrFFHgnkCnK # WAV/laxjHSJkzRNK06jD5KN/G2Osy587GXAWLaN76Y8mYMNJs5x3wwlBrJm0RyeJ # mWeETJOjxsFjW1+5LKhYv6fwiDxQcyJUoRKzJI27fYgDS+H+zIpa+uhy82Ah543z # i/HPyerp25TWAuVyR6mQICt7cne+4yjhtcjg0GXmnvm2+UVp54FGjesjwpSdbALl # OKdCre/JaNOkKoaRSsxm0UhNEyQarJIEf/dv0fTjsEpvNX2SMuLUGCm+n23wjXGN # fdnSGkoVe8hHxBtG80Zx8AMfKEmJoVsQw9rSg4HwQKOyrYPnLhHjb8ln43X+f3MN # gq9lDBIxH82LH2Q5JqQQe7S2UJycpYb+qj0xm7llH7Wl9VVKG6hRX/Cd7I1PQLEv # baPIrtye5TuR6uo0kn6HBB+Hd9RNu2PPHelmEFIGEuNaAPkyOt4FhKFIE/j0BTcg # mFVCNj6Os805ks0sjIBvpTU1DBtuqpLxdvvHOwxYKCNThTl70wfHJJEjumfvZ4qT # T+me7hRsd+8v1rRjxYGuJn2gqC7JL8miuJCYlZkn2DfMAunmF00U5ULe9KiCJ8V3 # kDfvO+CdnIN4MSlbtwt+eRSFCmJGGkzZ/jshVxPF3ZVirFu/undphYQnaEZDH+Xd # KsPOh8MekMgJ # =e55j # -----END PGP SIGNATURE----- # gpg: Signature made Fri 10 Mar 2023 22:08:35 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu: (28 commits) linux-user: fix bug about incorrect base addresss of gdt on i386 and x86_64 linux-user/sparc: Handle tag overflow traps linux-user/sparc: Handle floating-point exceptions linux-user/sparc: Handle unimplemented flush trap linux-user/sparc: Handle coprocessor disabled trap linux-user/sparc: Handle privilidged action trap linux-user/sparc: Handle priviledged opcode trap linux-user/sparc: Handle getcc, setcc, getpsr traps linux-user/sparc: Handle division by zero traps linux-user/sparc: Handle software breakpoint trap linux-user/sparc: Fix sparc64_{get, set}_context traps linux-user/sparc: Tidy window spill/fill traps linux-user/sparc: Use TT_TRAP for flush windows linux-user/sparc: Tidy syscall error return linux-user/sparc: Tidy syscall trap linux-user: Emulate CLONE_PIDFD flag in clone() linux-user: Add translation for argument of msync() linux-user: handle netlink flag NLA_F_NESTED linux-user: fix sockaddr_in6 endianness linux-user: Add strace for prlimit64() syscall ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-10linux-user: fix bug about incorrect base addresss of gdt on i386 and x86_64fanwj@mail.ustc.edu.cn
On linux user mode, CPUX86State::gdt::base from Different CPUX86State Objects have same value, It is incorrect! Every CPUX86State::gdt::base Must points to independent memory space. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1405 Signed-off-by: fanwenjie <fanwj@mail.ustc.edu.cn> Message-Id: <4172b90.58b08.18631b77860.Coremail.fanwj@mail.ustc.edu.cn> [lv: remove unnecessary casts, split overlong line] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle tag overflow trapsRichard Henderson
This trap is raised by taddcctv and tsubcctv insns. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-16-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle floating-point exceptionsRichard Henderson
Raise SIGFPE for ieee exceptions. The other types, such as FSR_FTT_UNIMPFPOP, should not appear, because we enable normal emulation of missing insns at the start of sparc_cpu_realizefn(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-15-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle unimplemented flush trapRichard Henderson
For sparc64, TT_UNIMP_FLUSH == TT_ILL_INSN, so this is already handled. For sparc32, the kernel uses SKIP_TRAP. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-14-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle coprocessor disabled trapRichard Henderson
Since qemu does not implement a sparc coprocessor, all such instructions raise this trap. Because of that, we never raise the coprocessor exception trap, which would be vector 0x28. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-13-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle privilidged action trapRichard Henderson
This is raised by using an %asi < 0x80 in user-mode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-12-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle priviledged opcode trapRichard Henderson
For the most part priviledged opcodes are ifdefed out of the user-only sparc translator, which will then incorrectly produce illegal opcode traps. But there are some code paths that properly raise TT_PRIV_INSN, so we must handle it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-11-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle getcc, setcc, getpsr trapsRichard Henderson
These are really only meaningful for sparc32, but they're still present for backward compatibility for sparc64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-10-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle division by zero trapsRichard Henderson
In addition to the hw trap vector, there is a software trap assigned for older sparc without hw division instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-9-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Handle software breakpoint trapRichard Henderson
This is 'ta 1' for both v9 and pre-v9. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Fix sparc64_{get, set}_context trapsRichard Henderson
These traps are present for sparc64 with ilp32, aka sparc32plus. Enabling them means adjusting the defines over in signal.c, and fixing an incorrect usage of abi_ulong when we really meant the full register, target_ulong. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Tidy window spill/fill trapsRichard Henderson
Add some macros to localize the hw difference between v9 and pre-v9. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230216054516.1267305-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Use TT_TRAP for flush windowsRichard Henderson
The v9 and pre-v9 code can be unified with this macro. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230216054516.1267305-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Tidy syscall error returnRichard Henderson
Reduce ifdefs with #define syscall_cc. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216054516.1267305-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-03-10linux-user/sparc: Tidy syscall trapRichard Henderson
Use TT_TRAP. For sparc32, 0x88 is the "Slowaris" system call, currently BAD_TRAP in the kernel's ttable_32.S. For sparc64, 0x110 is tl0_linux32, the sparc32 trap, now folded into the TARGET_ABI32 case via TT_TRAP. For sparc64, there does still exist trap 0x111 as tl0_oldlinux64, which was replaced by 0x16d as tl0_linux64 in 1998. Since no one has noticed, don't bother implementing it now. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230216054516.1267305-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-25 22:52:06 +0000