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2021-02-15linux-user/mips: Support the n32 ABI for the R5900Fredrik Noring
Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU supporting the n32 ABI. Signed-off-by: Fredrik Noring <noring@nocrew.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <5bea109f0c140da6a821aa7f9705d4b3717e86dc.1541701393.git.noring@nocrew.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: target: signal: Support TARGET_SS_AUTODISARMChen Gang
Add definitions to pass building. Signed-off-by: Chen Gang <chengang@emindsoft.com.cn> Message-Id: <20201008043105.21058-1-chengang@emindsoft.com.cn> [lv: added the definitions in linux-user/generic/signal.h too] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: add TARGET_SO_{DOMAIN,PROTOCOL}Jason A. Donenfeld
These were defined for other platforms but mistakenly left out of mips and generic, so this commit adds them to the places missing. Then it makes them be translated in getsockopt. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210204153925.2030606-1-Jason@zx2c4.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user/syscall: Fix do_ioctl_ifconf() for 64 bit targets.Stefan
The sizeof(struct ifreq) is 40 for 64 bit and 32 for 32 bit architectures. This structure contains a union of other structures, of which struct ifmap is the biggest for 64 bit architectures. Calling ioclt(…, SIOCGIFCONF, …) fills a struct sockaddr of that union, and do_ioctl_ifconf() only considered that struct sockaddr for the size of the union, which has the same size as struct ifmap on 32 bit architectures. So do_ioctl_ifconf() assumed a wrong size of 32 for struct ifreq instead of the correct size of 40 on 64 bit architectures. The fix makes do_ioctl_ifconf() handle struct ifmap as the biggest part of the union, treating struct ifreq with the correct size. Signed-off-by: Stefan <stefan-guix@vodafonemail.de> Message-Id: <60AA0765-53DD-43D1-A3D2-75F1778526F6@vodafonemail.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user/mmap: Avoid asserts for out of range mremap callsRichard Purdie
If mremap() is called without the MREMAP_MAYMOVE flag with a start address just before the end of memory (reserved_va) where new_size would exceed it (and GUEST_ADDR_MAX), the assert(end - 1 <= GUEST_ADDR_MAX) in  page_set_flags() would trigger. Add an extra guard to the guest_range_valid() checks to prevent this and avoid asserting binaries when reserved_va is set. This meant a bug I was seeing locally now gives the same behaviour  regardless of whether reserved_va is set or not. Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <70c46e7b999bafbb01d54bfafd44b420d0b782e9.camel@linuxfoundation.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: Fix loading of BSS segmentsGiuseppe Musacchio
Some ELF binaries encode the .bss section as an extension of the data ones by setting the segment p_memsz > p_filesz. Some other binaries take a different route and encode it as a stand-alone PT_LOAD segment with p_filesz = 0 and p_memsz > 0. Both the encodings are actually correct per ELF specification but the ELF loader had some troubles in handling the former: with the old logic it was very likely to get Qemu to crash in zero_bss when trying to access unmapped memory. zero_bss isn't meant to allocate whole zero-filled segments but to "complete" a previously mapped segment with the needed zero bits. The fix is pretty simple, if the segment is completely zero-filled we simply allocate one or more pages (according to p_memsz) and avoid calling zero_bss altogether. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Message-Id: <c9106487-dc4d-120a-bd48-665b3c617287@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: fix O_NONBLOCK in signalfd4() and eventfd2() syscallsHelge Deller
On the hppa target userspace binaries may call signalfd4() and eventfd2() with an old TARGET_O_NONBLOCK value of 000200004 instead of 000200000 for the "mask" syscall parameter, in which case the current emulation doesn't handle the translation to the native O_NONBLOCK value correctly. The 0x04 bit is not masked out before the new O_NONBLOCK bit is set and as such when calling the native syscall errors out with EINVAL. Fix this by introducing TARGET_O_NONBLOCK_MASK which is used to mask off all possible bits. This define defaults to TARGET_O_NONBLOCK when not defined otherwise, so for all other targets the implementation will behave as before. This patch needs to be applied on top of my previous two patches. Bug was found and patch was verified by using qemu-hppa as debian buildd server on x86_64. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210210061214.GA221322@ls3530.fritz.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: fix O_NONBLOCK usage for hppa targetHelge Deller
Historically the parisc linux port tried to be compatible with HP-UX userspace and as such defined the O_NONBLOCK constant to 0200004 to emulate separate NDELAY & NONBLOCK values. Since parisc was the only Linux platform which had two bits set, this produced various userspace issues. Finally it was decided to drop the (never completed) HP-UX compatibilty, which is why O_NONBLOCK was changed upstream to only have one bit set in future with this commit: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=75ae04206a4d0e4f541c1d692b7febd1c0fdb814 This patch simply adjusts the value for qemu-user too. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210201220551.GA8015@ls3530.fritz.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: Add missing TARGET___O_TMPFILE for hppa and alphaHelge Deller
The hppa and alpha targets miss the #define of the TARGET___O_TMPFILE and as such fail to run a trivial symlink command like ln -s /bin/bash /tmp which results in an -EINVAL return code. Adding the define fixes the problem. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210201155922.GA18291@ls3530.fritz.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user/signal: Decode waitid si_codeAlistair Francis
When mapping the host waitid status to the target status we previously just used decoding information in the status value. This doesn't follow what the waitid documentation describes, which instead suggests using the si_code value for the decoding. This results in the incorrect values seen when calling waitid. This is especially apparent on RV32 where all wait calls use waitid (see the bug case). This patch just passes the waitid status directly back to the guest. Buglink: https://bugs.launchpad.net/qemu/+bug/1906193 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Andreas K. Hüttel <dilfridge@gentoo.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1fb2d56aa23a81f4473e638abe9e2d78c09a3d5b.1611080607.git.alistair.francis@wdc.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user/mips64: Support o32 ABI syscallsPhilippe Mathieu-Daudé
o32 ABI syscalls start at offset 4000. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201119161710.1985083-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user/mips64: Restore setup_frame() for o32 ABIPhilippe Mathieu-Daudé
64-bit MIPS targets lost setup_frame() during the refactor in commit 8949bef18b9. Restore it declaring TARGET_ARCH_HAS_SETUP_FRAME, to be able to build the o32 ABI target. Fixes: 8949bef18b9 ("linux-user: move mips/mips64 signal.c parts to mips directory") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201119161710.1985083-2-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-05accel: replace struct CpusAccel with AccelOpsClassClaudio Fontana
This will allow us to centralize the registration of the cpus.c module accelerator operations (in accel/accel-softmmu.c), and trigger it automatically using object hierarchy lookup from the new accel_init_interfaces() initialization step, depending just on which accelerators are available in the code. Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c, kvm-accel-ops.c, etc, matching the object type names. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-18-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel: extend AccelState and AccelClass to user-modeClaudio Fontana
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [claudio: rebased on Richard's splitwx work] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-17-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-21linux-user: Remove obsolete F_SHLCK and F_EXLCK translationMichael Forney
These lock types are unsupported by Linux since v2.2[0][1] and always return EINVAL (except on SPARC up until v2.6, which just warned). musl libc does not define these constants, so just remove them from the translation cases. [0] https://github.com/mpe/linux-fullhistory/blob/v2.2.0/fs/locks.c#L322-L324 [1] https://github.com/mpe/linux-fullhistory/blob/v2.2.0/fs/locks.c#L429-L445 Signed-off-by: Michael Forney <mforney@mforney.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210114223602.9004-1-mforney@mforney.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-21linux-user: Add IPv6 options to do_print_sockopt()Shu-Chun Weng
Signed-off-by: Shu-Chun Weng <scw@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201218193213.3566856-5-scw@google.com> [lv: Add missing <linux/in6.h> include for IPV6_ADDR_PREFERENCES] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-20linux-user: add missing IPv6 get/setsockopt optionShu-Chun Weng
IPV6_ADDR_PREFERENCES (RFC5014: Source address selection) was not supported. Signed-off-by: Shu-Chun Weng <scw@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201218193213.3566856-4-scw@google.com> [PMD: Add missing <linux/in6.h> include for IPV6_ADDR_PREFERENCES] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-20linux-user: add missing UDP get/setsockopt optionShu-Chun Weng
SOL_UDP manipulate options at UDP level. All six options currently defined in linux source include/uapi/linux/udp.h take integer values. Signed-off-by: Shu-Chun Weng <scw@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201218193213.3566856-3-scw@google.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-20linux-user: Support F_ADD_SEALS and F_GET_SEALS fcntlsShu-Chun Weng
Also reorder blocks so that they are all in the same order everywhere. Signed-off-by: Shu-Chun Weng <scw@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201218193213.3566856-2-scw@google.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18riscv: Add semihosting support for user modeKito Cheng
This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210107170717.2098982-7-keithp@keithp.com> Message-Id: <20210108224256.2321-18-alex.bennee@linaro.org>
2021-01-18riscv: Add semihosting supportKeith Packard
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org>
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard
This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org>
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org>
2021-01-14target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé
Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé
The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé
The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé
Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé
Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
2021-01-07tcg: Add --accel tcg,split-wx propertyRichard Henderson
Plumb the value through to alloc_code_gen_buffer. This is not supported by any os or tcg backend, so for now enabling it will result in an error. Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-07linux-user: Conditionalize TUNSETVNETLERichard Henderson
This fixes the build for older ppc64 kernel headers. Fixes: 6addf06a3c4 Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-12-18linux-user/sparc: Handle tstate in sparc64_get/set_context()Peter Maydell
Correctly implement save/restore of the tstate field in sparc64_get_context() and sparc64_set_context(): * Don't use the CWP value from the guest in set_context * Construct and save a tstate value rather than leaving it as zero in get_context To do this we factor out the "calculate TSTATE value from CPU state" code from sparc_cpu_do_interrupt() into its own sparc64_tstate() function; that in turn requires us to move some of the function prototypes out from inside a CPU_NO_IO_DEFS ifdef guard. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201106152738.26026-5-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-18linux-user/sparc: Don't restore %g7 in sparc64_set_context()Peter Maydell
The kernel does not restore the g7 register in sparc64_set_context(); neither should we. (We still save it in sparc64_get_context().) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201106152738.26026-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-18linux-user/sparc: Remove unneeded checks of 'err' from sparc64_get_context()Peter Maydell
Unlike the kernel macros, our __get_user() and __put_user() do not return a failure code. Kernel code typically has a style of err |= __get_user(...); err |= __get_user(...); and then checking err at the end. In sparc64_get_context() our version of the code dropped the accumulating into err but left the "if (err) goto do_sigsegv" checks, which will never be taken. Delete unnecessary if()s. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201106152738.26026-3-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-18linux-user/sparc: Correct sparc64_get/set_context() FPU handlingPeter Maydell
The handling of the FPU state in sparc64_get_context() and sparc64_set_context() is not the same as what the kernel actually does: we unconditionally read and write the FP registers and the FSR, GSR and FPRS, but the kernel logic is more complicated: * in get_context the kernel has code for saving FPU registers, but it is hidden inside an "if (fenab) condition and the fenab flag is always set to 0 (inside an "#if 1" which has been in the kernel for over 15 years). So the effect is that the FPU state part is always written as zeroes. * in set_context the kernel looks at the fenab field in the structure from the guest, and only restores the state if it is set; it also looks at the structure's FPRS to see whether either the upper or lower or both halves of the register file have valid data. Bring our implementations into line with the kernel: * in get_context: - clear the entire target_ucontext at the top of the function (as the kernel does) - then don't write the FPU state, so those fields remain zero - this fixes Coverity issue CID 1432305 by deleting the code it was complaining about * in set_context: - check the fenab and the fpsr to decide which parts of the FPU data to restore, if any - instead of setting the FPU registers by doing two 32-bit loads and filling in the .upper and .lower parts of the CPU_Double union separately, just do a 64-bit load of the whole register at once. This fixes Coverity issue CID 1432303 because we now access the dregs[] part of the mcfpu_fregs union rather than the sregs[] part (which is not large enough to actually cover the whole of the data, so we were accessing off the end of sregs[]) We change both functions in a single commit to avoid potentially breaking bisection. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201106152738.26026-2-peter.maydell@linaro.org> [lv: fix FPRS_DU loop s/31/32/] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-18linux-user: Add most IFTUN ioctlsShu-Chun Weng
The three options handling `struct sock_fprog` (TUNATTACHFILTER, TUNDETACHFILTER, and TUNGETFILTER) are not implemented. Linux kernel keeps a user space pointer in them which we cannot correctly handle. Signed-off-by: Josh Kunz <jkz@google.com> Signed-off-by: Shu-Chun Weng <scw@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20200929014801.655524-1-scw@google.com> [lv: use 0 size in unlock_user()] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-18linux-user: Implement copy_file_rangeAndreas Schwab
Signed-off-by: Andreas Schwab <schwab@suse.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <mvm361eer3n.fsf@suse.de> [lv: copy back offset only if there is no error] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user: Add support for MIPS Loongson 2F/3APhilippe Mathieu-Daudé
Userland ELF binaries using Loongson SIMD instructions have the HWCAP_LOONGSON_MMI bit set [1]. Binaries compiled for Loongson 3A [2] have the HWCAP_LOONGSON_EXT bit set for the LQ / SQ instructions. [1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags") [2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214003215.344522-7-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user/elfload: Update HWCAP bits from linux 5.7Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214003215.344522-6-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macroPhilippe Mathieu-Daudé
ISA features are usually denoted in read-only bits from CPU registers. Add the GET_FEATURE_REG_EQU() macro which checks if a CPU register has bits set to a specific value. Use the macro to check the 'Architecture Revision' level of the Config0 register, which is '2' when the Release 6 ISA is implemented. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214003215.344522-5-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macroPhilippe Mathieu-Daudé
ISA features are usually denoted in read-only bits from CPU registers. Add the GET_FEATURE_REG_SET() macro which checks if a CPU register has bits set. Use the macro to check for MSA (which sets the MSAP bit of the Config3 register when the ASE implementation is present). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214003215.344522-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user/elfload: Rename MIPS GET_FEATURE() as GET_FEATURE_INSN()Philippe Mathieu-Daudé
We want to add macros similar to GET_FEATURE(). As this one use the 'insn_flags' field, rename it GET_FEATURE_INSN(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214003215.344522-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user/elfload: Move GET_FEATURE macro out of get_elf_hwcap() bodyPhilippe Mathieu-Daudé
As we are going to add more macros, keep the function body clear. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201214003215.344522-2-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-17linux-user/mmap.c: check range of mremap result in target address spaceTobias Koch
If mremap succeeds, an additional check is performed to ensure that the new address range fits into the target address space. This check was previously perfomed in host address space, with the upper bound fixed to abi_ulong. This patch replaces the static check with a call to `guest_range_valid`, performing the range check against the actual size of the target address space. It also moves the corresponding block to prevent it from being called incorrectly when the mapping itself fails. Signed-off-by: Tobias Koch <tobias.koch@nonterra.com> Message-Id: <20201028213833.26592-1-tobias.koch@nonterra.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-15linux-user: remove GNUC checkMarc-André Lureau
QEMU requires Clang or GCC, that define and support __GNUC__ extensions. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20201210134752.780923-13-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-15plugin: propagate errorsPaolo Bonzini
qemu_finish_machine_init currently can only exit QEMU if it fails. Prepare for giving it proper error propagation, and possibly for adding a plugin_add monitor command that calls an accelerator method. While at it, make all errors from plugin_load look the same. Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-12-13configure / meson: Move check for linux/btrfs.h to meson.buildThomas Huth
This check can be done in a much shorter way in meson.build. And while we're at it, rename the #define to HAVE_BTRFS_H to match the other HAVE_someheader_H symbols that we already have. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201118171052.308191-7-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-13configure / meson: Move check for sys/kcov.h to meson.buildThomas Huth
This check can be done in a much shorter way in meson.build. And while we're at it, rename the #define to HAVE_SYS_KCOV_H to match the other HAVE_someheader_H symbols that we already have. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201118171052.308191-6-thuth@redhat.com> [lv: s/signal/kcov/] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-11-23linux-user/arm: Deliver SIGTRAP for UDF patterns used as breakpointsPeter Maydell
The Linux kernel doesn't use the official bkpt insn for breakpoints; instead it uses three instructions in the guaranteed-to-UNDEF space, and generates SIGTRAP for these rather than the SIGILL that most UNDEF insns generate: https://elixir.bootlin.com/linux/v5.9.8/source/arch/arm/kernel/ptrace.c#L197 Make QEMU treat these insns specially too. The main benefit of this is that if you're running a debugger on a guest program that runs into a GCC __builtin_trap() or LLVM "trap because execution should never reach here" then you'll get the expected signal rather than a SIGILL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201117155634.6924-1-peter.maydell@linaro.org
2020-11-17linux-user,netlink: add IFLA_BRPORT_MRP_RING_OPEN, IFLA_BRPORT_MRP_IN_OPENLaurent Vivier
Fix "-d unimp" trace results: Unknown QEMU_IFLA_BRPORT type 35 Unknown QEMU_IFLA_BRPORT type 36 Also process IFLA_EXT_MASK to fix: Unknown target QEMU_IFLA type: 29 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201117111905.843925-1-laurent@vivier.eu>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-24 10:03:25 +0000