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2018-09-07target-ppc: Extend HWCAP2 bits for ISA 3.0Sandipan Das
This adds the HWCAP2 bit to detect if a linux user process is running on an ISA 3.0 compliant cpu like POWER9. This can be verified using a simple test program that prints the value in the auxiliary vector for AT_HWCAP2 as shown below. Before: $ qemu-ppc64le -cpu power8 test 0x8c000000 $ qemu-ppc64le -cpu power9 test 0x8c000000 After: $ qemu-ppc64le -cpu power8 test 0x8c000000 $ qemu-ppc64le -cpu power9 test 0x8c800000 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-08-24elf: Don't check FCR31_NAN2008 bit for nanoMIPSAleksandar Markovic
nanoMIPS is always NaN2008 compliant, and rules for checking FCR31's NAN2008 bit are obsoleted. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS tooAleksandar Markovic
Starting from nanoMIPS introduction, machine variant can be EM_MIPS or EM_NANOMIPS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement emulation of nanoMIPS LLWP/SCWP pairAleksandar Rikalo
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-23Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* x86 TCG fixes for 64-bit call gates (Andrew) * qumu-guest-agent freeze-hook tweak (Christian) * pm_smbus improvements (Corey) * Move validation to pre_plug for pc-dimm (David) * Fix memory leaks (Eduardo, Marc-André) * synchronization profiler (Emilio) * Convert the CPU list to RCU (Emilio) * LSI support for PPR Extended Message (George) * vhost-scsi support for protection information (Greg) * Mark mptsas as a storage device in the help (Guenter) * checkpatch tweak cherry-picked from Linux (me) * Typos, cleanups and dead-code removal (Julia, Marc-André) * qemu-pr-helper support for old libmultipath (Murilo) * Annotate fallthroughs (me) * MemoryRegionOps cleanup (me, Peter) * Make s390 qtests independent from libqos, which doesn't actually support it (me) * Make cpu_get_ticks independent from BQL (me) * Introspection fixes (Thomas) * Support QEMU_MODULE_DIR environment variable (ryang) # gpg: Signature made Thu 23 Aug 2018 17:46:30 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (69 commits) KVM: cleanup unnecessary #ifdef KVM_CAP_... target/i386: update MPX flags when CPL changes i2c: pm_smbus: Add the ability to force block transfer enable i2c: pm_smbus: Don't delay host status register busy bit when interrupts are enabled i2c: pm_smbus: Add interrupt handling i2c: pm_smbus: Add block transfer capability i2c: pm_smbus: Make the I2C block read command read-only i2c: pm_smbus: Fix the semantics of block I2C transfers i2c: pm_smbus: Clean up some style issues pc-dimm: assign and verify the "addr" property during pre_plug pc: drop memory region alignment check for 0 util/oslib-win32: indicate alignment for qemu_anon_ram_alloc() pc-dimm: assign and verify the "slot" property during pre_plug ipmi: Use proper struct reference for BT vmstate vhost-scsi: expose 't10_pi' property for VIRTIO_SCSI_F_T10_PI vhost-scsi: unify vhost-scsi get_features implementations vhost-user-scsi: move host_features into VHostSCSICommon cpus: allow cpu_get_ticks out of BQL cpus: protect TimerState writes with a spinlock seqlock: add QemuLockable support ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-23qom: convert the CPU list to RCUEmilio G. Cota
Iterating over the list without using atomics is undefined behaviour, since the list can be modified concurrently by other threads (e.g. every time a new thread is created in user-mode). Fix it by implementing the CPU list as an RCU QTAILQ. This requires a little bit of extra work to traverse list in reverse order (see previous patch), but other than that the conversion is trivial. Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <20180819091335.22863-12-cota@braap.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-08-21linux-user: Propagate goto fail to returnRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180818190118.12911-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-21linux-user: Propagate goto unimplemented to defaultRichard Henderson
There is no point in listing a syscall if you want the same effect as not listing it. In one less trivial case, the goto was demonstrably not reachable. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180818190118.12911-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-21linux-user: Propagate goto unimplemented_nowarn to returnRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180818190118.12911-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-21linux-user: Propagate goto efault to returnRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180818190118.12911-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-21linux-user: Relax single exit from "break"Richard Henderson
Transform outermost "break" to "return ret". If the immediately preceeding statement was an assignment to ret, return the value directly. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180818190118.12911-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-21linux-user: Split out do_syscall1Richard Henderson
There was supposed to be a single point of return for do_syscall so that tracing works properly. However, there are a few bugs in that area. It is significantly simpler to simply split out an inner function to enforce this. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180818190118.12911-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-21linux-user: Remove DEBUGRichard Henderson
This is redundant with both -strace and actual tracing. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180818190118.12911-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-08-20linux-user: add QEMU_IFLA_INFO_KIND nested type for tunLaurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180820171557.7734-5-laurent@vivier.eu>
2018-08-20linux-user: update netlink route typesLaurent Vivier
Add RTA_PREF and RTA_CACHEINFO. Fix following errors when we start gedit: Unknown host RTA type: 12 Unknown host RTA type: 20 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180820171557.7734-4-laurent@vivier.eu>
2018-08-20linux-user: introduce QEMU_RTA_* to use with rtattr_type_tLaurent Vivier
Following commit will introduce RTA_PREF that appears only with kernel v4.1. To avoid to manage a specific case for it, this patch introduces the full list of rtattr_type_t prefixed with QEMU_ (as we did for IFLA values) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180820171557.7734-3-laurent@vivier.eu> [lv: added more RTA_* from linux v4.18]
2018-08-20linux-user: fix recvmsg()/recvfrom() with netlink and MSG_TRUNCLaurent Vivier
If recvmsg()/recvfrom() are used with the MSG_TRUNC flag, they return the real length even if it was longer than the passed buffer. So when we translate the buffer we must check we don't go beyond the end of the buffer. Bug: https://github.com/vivier/qemu-m68k/issues/33 Reported-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180820171557.7734-2-laurent@vivier.eu>
2018-08-17linux-user: fix 32bit g2h()/h2g()Laurent Vivier
sparc32plus has 64bit long type but only 32bit virtual address space. For instance, "apt-get upgrade" failed because of a mmap()/msync() sequence. mmap() returned 0xff252000 but msync() used g2h(0xffffffffff252000) to find the host address. The "(target_ulong)" in g2h() doesn't fix the address because it is 64bit long. This patch introduces an "abi_ptr" that is set to uint32_t if the virtual address space is addressed using 32bit in the linux-user case. It stays set to target_ulong with softmmu case. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180814171217.14680-1-laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [lv: added "%" in TARGET_ABI_FMT_ptr "%"PRIx64]
2018-08-16Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' ↵Peter Maydell
into staging MIPS queue Aug 16, 2018 # gpg: Signature made Thu 16 Aug 2018 18:19:36 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-2018: qemu-doc: Amend MIPS-related items linux-user: Add preprocessor availability control to some syscalls linux-user: Update MIPS syscall numbers up to kernel 4.18 headers elf: Add ELF flags for MIPS machine variants elf: Remove duplicate preprocessor constant definition target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 target/mips: Don't update BadVAddr register in Debug Mode target/mips: Implement CP0 Config1.WR bit functionality target/mips: Add CP0 BadInstrX register target/mips: Update some CP0 registers bit definitions target/mips: Fix two instances of shadow variables target/mips: Mark switch fallthroughs with interpretable comments target/mips: Avoid case statements formulated by ranges - part 2 target/mips: Avoid case statements formulated by ranges - part 1 MAINTAINERS: Update target/mips maintainer's email addresses Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16linux-user: Add preprocessor availability control to some syscallsAleksandar Rikalo
Add ability to target platforms to individually include user-mode support for system calls from "stat" group of system calls. This change is related to new nanoMIPS platform in the sense that it supports a different set of "stat" system calls than any other target. nanoMIPS does not support structures stat and stat64 at all. Also, support for certain number of other system calls is dropped in nanoMIPS (those are most of the time obsoleted system calls). Without this patch, build for nanoMIPS would fail. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Update MIPS syscall numbers up to kernel 4.18 headersAleksandar Markovic
Synchronize content of linux-user/mips/syscall_nr.h and linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers. This adds 9 new syscall numbers, the last being NR_io_pgetevents. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16target/arm: Add sve-max-vq cpu property to -cpu maxRichard Henderson
This allows the default (and maximum) vector length to be set from the command-line. Which is extraordinarily helpful in debugging problems depending on vector length without having to bake knowledge of PR_SET_SVE_VL into every guest binary. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-31linux-user: ppc64: don't use volatile register during safe_syscallShivaprasad G Bhat
r11 is a volatile register on PPC as per calling conventions. The safe_syscall code uses it to check if the signal_pending is set during the safe_syscall. When a syscall is interrupted on return from signal handling, the r11 might be corrupted before we retry the syscall leading to a crash. The registers r0-r13 are not to be used here as they have volatile/designated/reserved usages. Change the code to use r14 which is non-volatile. Use SP+16 which is a slot for LR, for save/restore of previous value of r14. SP+16 can be used, as LR is preserved across the syscall. Steps to reproduce: On PPC host, issue `qemu-x86_64 /usr/bin/cc -E -` Attempt Ctrl-C, the issue is reproduced. Reference: https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html#REG https://openpowerfoundation.org/wp-content/uploads/2016/03/ABI64BitOpenPOWERv1.1_16July2015_pub4.pdf Signed-off-by: Shivaprasad G Bhat <sbhat@linux.vnet.ibm.com> Tested-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <153301568965.30312.10498134581068746871.stgit@dhcp-9-109-246-16> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-31linux-user/mmap.c: handle invalid len maps correctlyAlex Bennée
I've slightly re-organised the check to more closely match the sequence that the kernel uses in do_mmap(). We check for both the zero case (EINVAL) and the overflow length case (ENOMEM). Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: umarcor <1783362@bugs.launchpad.net> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180730134321.19898-2-alex.bennee@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-22linux-user/ppc: Implement swapcontext syscallRichard Henderson
This allows the tests generated by debian-powerpc-user-cross to function properly, especially tests/test-coroutine. Technically this syscall is available to both ppc32 and ppc64, but only ppc32 glibc actually uses it. Thus the ppc64 path is untested. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180718200648.22529-1-richard.henderson@linaro.org>
2018-07-22linux-user: fix ELF load alignment errorLaurent Vivier
When we try to use some targets on ppc64, it can happen the target doesn't support the host page size to align ELF load sections and fails with: ELF load command alignment not page-aligned Since commit a70daba3771 ("linux-user: Tell guest about big host page sizes") the host page size is used to align ELF sections, but this doesn't work if the alignment required by the load section is smaller than the host one. For these cases, we continue to use the TARGET_PAGE_SIZE instead of the host one. I have tested this change on ppc64, and it fixes qemu linux-user for: s390x, m68k, i386, arm, aarch64, hppa and I have tested it doesn't break the following targets: x86_64, mips64el, sh4 mips and mipsel abort, but I think for another reason. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [lv: fixed "info->alignment = 0"] Message-Id: <20180716195349.29959-1-laurent@vivier.eu>
2018-07-15Zero out the host's `msg_control` bufferJonas Schievink
If this is not done, qemu would drop any control message after the first one. This is because glibc's `CMSG_NXTHDR` macro accesses the uninitialized cmsghdr's length field in order to find out if the message fits into the `msg_control` buffer, wrongly assuming that it doesn't because the length field contains garbage. Accessing the length field is fine for completed messages we receive from the kernel, but is - as far as I know - not needed since the kernel won't return such an invalid cmsghdr in the first place. This is tracked as this glibc bug: https://sourceware.org/bugzilla/show_bug.cgi?id=13500 It's probably also a good idea to bail with an error if `CMSG_NXTHDR` returns NULL but `TARGET_CMSG_NXTHDR` doesn't (ie. we still expect cmsgs). Signed-off-by: Jonas Schievink <jonasschievink@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180711221244.31869-1-jonasschievink@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-15linux-user: fix mmap_find_vma_reserved()Laurent Vivier
The value given by mmap_find_vma_reserved() is used with mmap(), so it is needed to be aligned with the host page size. Since commit 18e80c55bb, reserved_va is only aligned to TARGET_PAGE_SIZE, and it works well if this size is greater or equal to the host page size. But ppc64 hosts have 64kB page size and when we start a 4kiB page size guest (like i386), it fails when it tries to mmap the stack: mmap stack: Invalid argument Fixes: 18e80c55bb (linux-user: Tidy and enforce reserved_va initialization) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180714193553.30846-1-laurent@vivier.eu>
2018-07-15linux-user: convert remaining fcntl() to safe_fcntl()Laurent Vivier
Commit 435da5e709 didn't convert a fcntl() call to safe_fcntl() for TARGET_NR_fcntl64 case. There is no reason to not use it in this case. Fixes: 435da5e709 linux-user: Use safe_syscall wrapper for fcntl Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180713125805.10749-1-laurent@vivier.eu>
2018-07-15linux-user: ppc64: use the correct values for F_*LK64sShivaprasad G Bhat
Qemu includes the glibc headers for the host defines and target headers are part of the qemu source themselves. The glibc has the F_GETLK64, F_SETLK64 and F_SETLKW64 defined to 12, 13 and 14 for all archs in sysdeps/unix/sysv/linux/bits/fcntl-linux.h. The linux kernel generic definition for F_*LK is 5, 6 & 7 and F_*LK64* is 12,13, and 14 as seen in include/uapi/asm-generic/fcntl.h. On 64bit machine, by default the kernel assumes all F_*LK to 64bit calls and doesnt support use of F_*LK64* as can be seen in include/linux/fcntl.h in linux source. On x86_64 host, the values for F_*LK64* are set to 5, 6 and 7 explicitly in /usr/include/x86_64-linux-gnu/bits/fcntl.h by the glibc. Whereas, a PPC64 host doesn't have such a definition in /usr/include/powerpc64le-linux-gnu/bits/fcntl.h by the glibc. So, the sources on PPC64 host sees the default value of F_*LK64* as 12, 13 & 14(fcntl-linux.h). Since the 64bit kernel doesnt support 12, 13 & 14; the glibc fcntl syscall implementation(__libc_fcntl*(), __fcntl64_nocancel) does the F_*LK64* value convertion back to F_*LK* values on PPC64 as seen in sysdeps/unix/sysv/linux/powerpc/powerpc64/sysdep.h with FCNTL_ADJUST_CMD() macro. Whereas on x86_64 host the values for F_*LK64* are set to 5, 6 and 7 and no adjustments are needed. Since qemu doesnt use the glibc fcntl, but makes the safe_syscall* on its own, the PPC64 qemu is calling the syscall with 12, 13, and 14(without adjustment) and they all fail. The fcntl calls to F_GETLK/F_SETLK|W all fail by all pplications run on PPC64 host user emulation. The fix here could be to see why on PPC64 the glibc is still keeping F_*LK64* different from F_*LK and why adjusting them to 5, 6 and 7 before the syscall for PPC only. See if we can make the /usr/include/powerpc64le-linux-gnu/bits/fcntl.h to have the values 5, 6 & 7 just like x86_64 and remove the adjustment code in glibc. That way, qemu sources see the kernel supported values in glibc headers. OR On PPC64 host, qemu sources see both F_*LK & F_*LK64* as same and set to 12, 13 and 14 because __USE_FILE_OFFSET64 is defined in qemu sources(also refer sysdeps/unix/sysv/linux/bits/fcntl-linux.h). Do the value adjustment just like it is done by glibc source by using F_GETLK value of 5. That way, we make the syscalls with the actual supported values in Qemu. The patch is taking this approach. Signed-off-by: Shivaprasad G Bhat <sbhat@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <153148521235.87746.14142430397318741182.stgit@lep8c.aus.stglabs.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-09linux-user: Report error message on stderr, rather than stdoutPhilippe Mathieu-Daudé
Code change produced with: git ls-files linux-user | \ xargs sed -i -E 's/(\s+)printf\s*\(("Unhandled.*)\);/\1fprintf(stderr, \2);/g' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180706155127.7483-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-09linux-user: Do not report "syscall not implemented" by defaultPhilippe Mathieu-Daudé
This can still be reported using the "-d unimp" command line option. Code change produced with: git ls-files linux-user | \ xargs sed -i -E 's/fprintf\(stderr,\s?(".*not implemented\\n")\);/qemu_log_mask(LOG_UNIMP, \1);/g' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180706155127.7483-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-09linux-user: Do not report "Unsupported syscall" by defaultPhilippe Mathieu-Daudé
This can still be reported using the "-d unimp" command line option. Fixes: https://bugs.launchpad.net/qemu/+bug/1777226 Reported-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180706155127.7483-2-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-05linux-user: add gcov support to preexit_cleanupAlex Bennée
As we don't always take the normal exit path when running a guest we can skip the normal exit destructors where gcov normally dumps it's info. The GCC manual suggests long running programs use __gcov_dump() to flush out the coverage state periodically so we use that here. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-07-05linux-user: introduce preexit_cleanupAlex Bennée
To avoid repeating ourselves move our preexit clean-up code into a helper function. I figured the continuing effort to split of the syscalls made it worthwhile creating a new file for it now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu>
2018-07-04Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging Some strace cleanups Minor fixes for setsockopt() and netlink Manage 'F' flag with qemu-binfmt-conf.sh # gpg: Signature made Tue 03 Jul 2018 17:34:20 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-3.0-pull-request: linux-user/strace: Improve recvmsg() output linux-user/strace: Improve capget()/capset() output linux-user: update do_setsockopt() linux-user: add netlink CARRIER_UP_COUNT/CARRIER_DOWN_COUNT qemu-binfmt-conf.sh: allow to provide a suffix to the interpreter name qemu-binfmt-conf.sh: add persistent (F) flags qemu-binfmt-conf.sh: cleanup --credential Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-03Merge remote-tracking branch 'remotes/shorne/tags/pull-or-20180703' into stagingPeter Maydell
OpenRISC cleanups and Fixes for QEMU 3.0 Mostly patches from Richard Henderson fixing multiple things: * Fix singlestepping in GDB. * Use more TB linking. * Fixes to exit TB after updating SPRs to enable registering of state changes. * Significant optimizations and refactors to the TLB * Split out disassembly from translation. * Add qemu-or1k to qemu-binfmt-conf.sh. * Implement signal handling for linux-user. Then there are a few fixups from me: * Fix delay slot detections to match hardware, this was masking a bug in the linus kernel. * Fix stores to the PIC mask register # gpg: Signature made Tue 03 Jul 2018 14:44:10 BST # gpg: using RSA key C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * remotes/shorne/tags/pull-or-20180703: (25 commits) target/openrisc: Fix writes to interrupt mask register target/openrisc: Fix delay slot exception flag to match spec linux-user: Fix struct sigaltstack for openrisc linux-user: Implement signals for openrisc target/openrisc: Add support in scripts/qemu-binfmt-conf.sh target/openrisc: Reorg tlb lookup target/openrisc: Increase the TLB size target/openrisc: Stub out handle_mmu_fault for softmmu target/openrisc: Use identical sizes for ITLB and DTLB target/openrisc: Fix cpu_mmu_index target/openrisc: Fix tlb flushing in mtspr target/openrisc: Reduce tlb to a single dimension target/openrisc: Merge mmu_helper.c into mmu.c target/openrisc: Remove indirect function calls for mmu target/openrisc: Merge tlb allocation into CPUOpenRISCState target/openrisc: Form the spr index from tcg target/openrisc: Exit the TB after l.mtspr target/openrisc: Split out is_user target/openrisc: Link more translation blocks target/openrisc: Fix singlestep_enabled ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-03linux-user/strace: Improve recvmsg() outputPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-By: Guido Günther <agx@sigxcpu.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180628034652.24152-7-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-03linux-user/strace: Improve capget()/capset() outputPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-By: Guido Günther <agx@sigxcpu.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180628034652.24152-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-03Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180703' ↵Peter Maydell
into staging ppc patch queue 2018-07-03 Here's a last minue pull request before today's soft freeze. Ideally I would have sent this earlier, but I was waiting for a couple of extra fixes I knew were close. And the freeze crept up on me, like always. Most of the changes here are bugfixes in any case. There are some cleanups as well, which have been in my staging tree for a little while. There are a couple of truly new features (some extensions to the sam460ex platform), but these are low risk, since they only affect a new and not really stabilized machine type anyway. Higlights are: * Mac platform improvements from Mark Cave-Ayland * Sam460ex improvements from BALATON Zoltan et al. * XICS interrupt handler cleanups from Cédric Le Goater * TCG improvements for atomic loads and stores from Richard Henderson * Assorted other bugfixes # gpg: Signature made Tue 03 Jul 2018 06:55:22 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.0-20180703: (35 commits) ppc: Include vga cirrus card into the compiling process target/ppc: Relax reserved bitmask of indexed store instructions target/ppc: set is_jmp on ppc_tr_breakpoint_check spapr: compute default value of "hpt-max-page-size" later target/ppc/kvm: don't pass cpu to kvm_get_smmu_info() target/ppc/kvm: get rid of kvm_get_fallback_smmu_info() ppc440_uc: Basic emulation of PPC440 DMA controller sam460ex: Add RTC device hw/timer: Add basic M41T80 emulation ppc4xx_i2c: Rewrite to model hardware more closely hw/ppc: Give sam46ex its own config option fpu_helper.c: fix setting FPSCR[FI] bit target/ppc: Implement the rest of gen_st_atomic target/ppc: Implement the rest of gen_ld_atomic target/ppc: Use atomic min/max helpers target/ppc: Use MO_ALIGN for EXIWX and ECOWX target/ppc: Split out gen_st_atomic target/ppc: Split out gen_ld_atomic target/ppc: Split out gen_load_locked target/ppc: Tidy gen_conditional_store ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/ppc/spapr.c
2018-07-03linux-user: Fix struct sigaltstack for openriscRichard Henderson
Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2018-07-03linux-user: Implement signals for openriscRichard Henderson
All of the existing code was boilerplate from elsewhere, and would crash the guest upon the first signal. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> --- v2: Add a comment to the new definition of target_pt_regs. Install the signal mask into the ucontext. v3: Incorporate feedback from Laurent.
2018-07-03target/ppc: Remove POWERPC_EXCP_STCXRichard Henderson
Always use the gen_conditional_store implementation that uses atomic_cmpxchg. Make sure and clear reserve_addr across most interrupts crossing the cpu_loop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-07-02linux-user: update do_setsockopt()Laurent Vivier
add IPV6_MULTICAST_HOPS and IPV6_MULTICAST_LOOP that need 32bit value conversion Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180627212152.26525-3-laurent@vivier.eu>
2018-07-02linux-user: add netlink CARRIER_UP_COUNT/CARRIER_DOWN_COUNTLaurent Vivier
Error is reported with libuv test suite: not ok 311 - udp_multicast_interface6 # exit code 134 # Output from process `udp_multicast_interface6`: # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 # Unknown host QEMU_IFLA type: 47 # Unknown host QEMU_IFLA type: 48 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180627212152.26525-2-laurent@vivier.eu>
2018-07-02linux-user: Use the IEC binary prefix definitionsPhilippe Mathieu-Daudé
It eases code review, unit is explicit. Patch generated using: $ git grep -n '[<>][<>]= ?[1-5]0' and modified manually. Suggested-by: Eric Blake <eblake@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180625124238.25339-46-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-29target/arm: Implement ARMv8.2-DotProdRichard Henderson
We've already added the helpers with an SVE patch, all that remains is to wire up the aa64 and aa32 translators. Enable the feature within -cpu max for CONFIG_USER_ONLY. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Enable SVE for aarch64-linux-userRichard Henderson
Enable ARM_FEATURE_SVE for the generic "max" cpu. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-28move public invalidate APIs out of translate-all.{c,h}, clean upPaolo Bonzini
Place them in exec.c, exec-all.h and ram_addr.h. This removes knowledge of translate-all.h (which is an internal header) from several files outside accel/tcg and removes knowledge of AddressSpace from translate-all.c (as it only operates on ram_addr_t). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-06-15tcg: remove tb_lockEmilio G. Cota
Use mmap_lock in user-mode to protect TCG state and the page descriptors. In !user-mode, each vCPU has its own TCG state, so no locks needed. Per-page locks are used to protect the page descriptors. Per-TB locks are used in both modes to protect TB jumps. Some notes: - tb_lock is removed from notdirty_mem_write by passing a locked page_collection to tb_invalidate_phys_page_fast. - tcg_tb_lookup/remove/insert/etc have their own internal lock(s), so there is no need to further serialize access to them. - do_tb_flush is run in a safe async context, meaning no other vCPU threads are running. Therefore acquiring mmap_lock there is just to please tools such as thread sanitizer. - Not visible in the diff, but tb_invalidate_phys_page already has an assert_memory_lock. - cpu_io_recompile is !user-only, so no mmap_lock there. - Added mmap_unlock()'s before all siglongjmp's that could be called in user-mode while mmap_lock is held. + Added an assert for !have_mmap_lock() after returning from the longjmp in cpu_exec, just like we do in cpu_exec_step_atomic. Performance numbers before/after: Host: AMD Opteron(tm) Processor 6376 ubuntu 17.04 ppc64 bootup+shutdown time 700 +-+--+----+------+------------+-----------+------------*--+-+ | + + + + + *B | | before ***B*** ** * | |tb lock removal ###D### *** | 600 +-+ *** +-+ | ** # | | *B* #D | | *** * ## | 500 +-+ *** ### +-+ | * *** ### | | *B* # ## | | ** * #D# | 400 +-+ ** ## +-+ | ** ### | | ** ## | | ** # ## | 300 +-+ * B* #D# +-+ | B *** ### | | * ** #### | | * *** ### | 200 +-+ B *B #D# +-+ | #B* * ## # | | #* ## | | + D##D# + + + + | 100 +-+--+----+------+------------+-----------+------------+--+-+ 1 8 16 Guest CPUs 48 64 png: https://imgur.com/HwmBHXe debian jessie aarch64 bootup+shutdown time 90 +-+--+-----+-----+------------+------------+------------+--+-+ | + + + + + + | | before ***B*** B | 80 +tb lock removal ###D### **D +-+ | **### | | **## | 70 +-+ ** # +-+ | ** ## | | ** # | 60 +-+ *B ## +-+ | ** ## | | *** #D | 50 +-+ *** ## +-+ | * ** ### | | **B* ### | 40 +-+ **** # ## +-+ | **** #D# | | ***B** ### | 30 +-+ B***B** #### +-+ | B * * # ### | | B ###D# | 20 +-+ D ##D## +-+ | D# | | + + + + + + | 10 +-+--+-----+-----+------------+------------+------------+--+-+ 1 8 16 Guest CPUs 48 64 png: https://imgur.com/iGpGFtv The gains are high for 4-8 CPUs. Beyond that point, however, unrelated lock contention significantly hurts scalability. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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