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2020-04-07linux-user: more debug for init_guest_spaceAlex Bennée
Searching for memory space can cause problems so lets extend the CPU_LOG_PAGE output so you can watch init_guest_space fail to allocate memory. A more involved fix is actually required to make this function play nicely with the large guard pages the sanitiser likes to use. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20200403191150.863-5-alex.bennee@linaro.org>
2020-03-20linux-user: Add AT_EXECFN auxvalLirong Yuan
This change adds the support for AT_EXECFN auxval. Signed-off-by: Lirong Yuan <yuanzi@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20200302193153.66415-1-yuanzi@google.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-02-28target/arm: Implement v8.4-RCPCPeter Maydell
The v8.4-RCPC extension implements some new instructions: * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW * STLUR, STLURB, STLURH These are all in a new subgroup of encodings that sits below the top-level "Loads and Stores" group in the Arm ARM. The STLUR* instructions have standard store-release semantics; the LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose to implement them as the slightly stronger Load-Acquire. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224172846.13053-4-peter.maydell@linaro.org
2020-02-28target/arm: Implement v8.3-RCPCPeter Maydell
The v8.3-RCPC extension implements three new load instructions which provide slightly weaker consistency guarantees than the existing load-acquire operations. For QEMU we choose to simply implement them with a full LDAQ barrier. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224172846.13053-3-peter.maydell@linaro.org
2020-02-28linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAPRichard Henderson
Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-21target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registersPeter Maydell
Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200214175116.9164-2-peter.maydell@linaro.org
2020-01-22linux-user: Reserve space for brkRichard Henderson
With bad luck, we can wind up with no space at all for brk, which will generally cause the guest malloc to fail. This bad luck is easier to come by with ET_DYN (PIE) binaries, where either the stack or the interpreter (ld.so) gets placed immediately after the main executable. But there's nothing preventing this same thing from happening with ET_EXEC (normal) binaries, during probe_guest_base(). In both cases, reserve some extra space via mmap and release it back to the system after loading the interpreter and allocating the stack. The choice of 16MB is somewhat arbitrary. It's enough for libc to get going, but without being so large that 32-bit guests or 32-bit hosts are in danger of running out of virtual address space. It is expected that libc will be able to fall back to mmap arenas after the limited brk space is exhausted. Launchpad: https://bugs.launchpad.net/qemu/+bug/1749393 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200117230245.5040-1-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-01-22linux-user:Fix align mistake when mmap guest spaceXinyu Li
In init_guest_space, we need to mmap guest space. If the return address of first mmap is not aligned with align, which was set to MAX(SHMLBA, qemu_host_page_size), we need unmap and a new mmap(space is larger than first size). The new size is named real_size, which is aligned_size + qemu_host_page_size. alugned_size is the guest space size. And add a qemu_host_page_size to avoid memory error when we align real_start manually (ROUND_UP(real_start, align)). But when SHMLBA > qemu_host_page_size, the added size will smaller than the size to align, which can make a mistake(in a mips machine, it appears). So change real_size from aligned_size +qemu_host_page_size to aligned_size + align will solve it. Signed-off-by: Xinyu Li <precinct@mail.ustc.edu.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191213022919.5934-1-precinct@mail.ustc.edu.cn> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-12-16target/arm: Add support for DC CVAP & DC CVADP insBeata Michalska
ARMv8.2 introduced support for Data Cache Clean instructions to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence) - DV CVADP. Both specify conceptual points in a memory system where all writes that are to reach them are considered persistent. The support provided considers both to be actually the same so there is no distinction between the two. If none is available (there is no backing store for given memory) both will result in Data Cache Clean up to the point of coherency. Otherwise sync for the specified range shall be performed. Signed-off-by: Beata Michalska <beata.michalska@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191121000843.24844-5-beata.michalska@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-11linux-user: Support gdb 'qOffsets' query for ELFJosh Kunz
This is needed to support debugging PIE ELF binaries running under QEMU user mode. Currently, `code_offset` and `data_offset` remain unset for all ELF binaries, so GDB is unable to correctly locate the position of the binary's text and data. The fields `code_offset`, and `data_offset` were originally added way back in 2006 to support debugging of bFMT executables (978efd6aac6), and support was just never added for ELF. Since non-PIE binaries are loaded at exactly the address specified in the binary, GDB does not need to relocate any symbols, so the buggy behavior is not normally observed. http://sourceware.org/gdb/onlinedocs/gdb/General-Query-Packets.html#index-qOffsets-packet Buglink: https://bugs.launchpad.net/qemu/+bug/1528239 Signed-off-by: Josh Kunz <jkz@google.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190816233422.16715-1-jkz@google.com> [lv: added link to documentation] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-09-10linux-user: Add AT_HWCAP2 for aarch64-linux-userRichard Henderson
Add the HWCAP2_* bits from kernel version v5.3-rc3. Enable the bits corresponding to ARMv8.5-CondM and ARMv8.5-FRINT. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20190809171156.3476-1-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-08-16Include qemu/queue.h slightly lessMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-20-armbru@redhat.com>
2019-06-24linux-user: update PPC64 HWCAP2 feature listLaurent Vivier
QEMU_PPC_FEATURE2_VEC_CRYPTO enables the use of VSX instructions in libcrypto that are accelerated by the TCG vector instructions now. QEMU_PPC_FEATURE2_DARN allows to use the new builtin qemu_guest_getrandom() function. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190609143521.19374-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-07linux-user: elf: ELF_HWCAP for s390xDavid Hildenbrand
Let's add all HWCAPs that we can support under TCG right now, when the respective CPU facilities are enabled. Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Cornelia Huck <cohuck@redhat.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Richard Henderson <richard.henderson@linaro.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-24Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging Add /proc/hardware and /proc/cpuinfo, update SIOCXXX ioctls, fix shmat emulation, add nanoseconds in stat, init field fp_abi on mips # gpg: Signature made Fri 24 May 2019 12:24:36 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-4.1-pull-request: linux-user: Pass through nanosecond timestamp components for stat syscalls linux-user: Align mmap_find_vma to host page size linux-user: Fix shmat emulation by honoring host SHMLBA linux-user: Sanitize interp_info and, for mips only, init field fp_abi linux-user: Add support for SIOC<G|S>IFPFLAGS ioctls for all targets linux-user: Add support for SIOCSPGRP ioctl for all targets linux-user: Fix support for SIOCATMARK and SIOCGPGRP ioctls for xtensa linux-user: add pseudo /proc/hardware for m68k linux-user: add pseudo /proc/cpuinfo for sparc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-24linux-user: Fix shmat emulation by honoring host SHMLBARichard Henderson
For those hosts with SHMLBA > getpagesize, we don't automatically select a guest address that is compatible with the host. We can achieve this by boosting the alignment of guest_base and by adding an extra alignment argument to mmap_find_vma. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190519201953.20161-13-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-05-22linux-user: Sanitize interp_info and, for mips only, init field fp_abiDaniel Santos
Sanitize interp_info structure in load_elf_binary() and, for MIPS only, init its field fp_abi to MIPS_ABI_FP_UNKNOWN. This fixes appearances of "Unexpected FPU mode" message in some MIPS use cases. Currently, this bug is a complete stopper for some MIPS binaries. In load_elf_binary(), struct image_info interp_info is used without being properly initialized. One result is that when the ELF's program header doesn't contain an entry for the ABI flags, then the value of the struct image_info's fp_abi field is set to whatever happened to be in stack memory at the time. Backporting to 4.0 and, if possible, to 3.1 is recommended. Fixes: https://bugs.launchpad.net/qemu/+bug/1825002 Signed-off-by: Daniel Santos <daniel.santos@pobox.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1558282527-22183-6-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-05-22linux-user: Use qemu_guest_getrandom_nofail for AT_RANDOMRichard Henderson
Use a better interface for random numbers than rand * 16. Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-10linux-user: elf: Map empty PT_LOAD segmentsGiuseppe Musacchio
Some PT_LOAD segments may be completely zeroed out and their p_filesize is zero, in that case the loader should just allocate a page that's at least p_memsz bytes large (plus eventual alignment padding). Calling zero_bss does this job for us, all we have to do is make sure we don't try to mmap a zero-length page. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20190503122007.lkjsvztgt4ycovac@debian> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-05-09linux-user/elfload: Fix GCC 9 build warningsAlistair Francis
Fix this warning when building with GCC9 on Fedora 30: In function ‘strncpy’, inlined from ‘fill_psinfo’ at /home/alistair/qemu/linux-user/elfload.c:3208:12, inlined from ‘fill_note_info’ at /home/alistair/qemu/linux-user/elfload.c:3390:5, inlined from ‘elf_core_dump’ at /home/alistair/qemu/linux-user/elfload.c:3539:9: /usr/include/bits/string_fortified.h:106:10: error: ‘__builtin_strncpy’ specified bound 16 equals destination size [-Werror=stringop-truncation] 106 | return __builtin___strncpy_chk (__dest, __src, __len, __bos (__dest)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <c4d2b1de9efadcf1c900b91361af9302823a72a9.1556666645.git.alistair.francis@wdc.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-03-07linux-user: Fix ELF_PLATFORM for aarch64_be-linux-userRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190212074840.13542-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-03-07linux-user: Add ELF_PLATFORM for armRichard Henderson
The 32-bit kernel has strings for v4, v5, v6, v7, v7m. The 64-bit kernel, in compat mode, has strings for v8. Fixes: https://bugs.launchpad.net/bugs/1813034 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190212074840.13542-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-03-05target/arm: Implement ARMv8.4-CondMRichard Henderson
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed up block comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05target/arm: Implement ARMv8.0-SBRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVTRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190219222952.22183-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-15linux-user/elfload: enable HWCAP_CPUID for AArch64Alex Bennée
Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190205190224.2198-6-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01aarch64-linux-user: Enable HWCAP bits for PAuthRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-01aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-11qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini
Most list head structs need not be given a name. In most cases the name is given just in case one is going to use QTAILQ_LAST, QTAILQ_PREV or reverse iteration, but this does not apply to lists of other kinds, and even for QTAILQ in practice this is only rarely needed. In addition, we will soon reimplement those macros completely so that they do not need a name for the head struct. So clean up everything, not giving a name except in the rare case where it is necessary. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-29linux-user: Read and set FP ABI value from MIPS abiflagsStefan Markovic
Set fp_abi and interp_fp_abi values to current fp_abi value read from MIPS.abiflags. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29linux-user: Extract MIPS abiflags from ELF fileStefan Markovic
Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-24target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 testRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24target/arm: Convert sve from feature bit to aa64pfr0 testRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24target/arm: Convert division from feature bits to isar0 testsRichard Henderson
Both arm and thumb2 division are controlled by the same ISAR field, which takes care of the arm implies thumb case. Having M imply thumb2 division was wrong for cortex-m0, which is v6m and does not have thumb2 at all, much less thumb2 division. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-24target/arm: Convert v8 extensions from feature bits to isar testsRichard Henderson
Most of the v8 extensions are self-contained within the ISAR registers and are not implied by other feature bits, which makes them the easiest to convert. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181016223115.24100-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-28Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/linux-user-for-3.1-pull-request' into staging - some fixes for setrlimit() and write() - fixes ELF loader when host page size is greater than target page size - add SO_LINGER to getsockopt()/setsockopt() - move TargetFdTrans from syscall.c v2: add "#include <linux/netlink.h>" in linux-user/fd-trans.c # gpg: Signature made Tue 25 Sep 2018 21:51:13 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-3.1-pull-request: linux-user: do setrlimit selectively linux-user: write(fd, NULL, 0) parity with linux's treatment of same linux-user: elf: mmap all the target-pages of hostpage for data segment linux-user: add SO_LINGER to {g,s}etsockopt linux-user: move TargetFdTrans functions to their own file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25linux-user: elf: mmap all the target-pages of hostpage for data segmentShivaprasad G Bhat
If the hostpage size is greater than the TARGET_PAGESIZE, the target-pages of size TARGET_PAGESIZE are marked valid only till the length requested during the elfload. The glibc attempts to consume unused space in the last page of data segment(__libc_memalign() in elf/dl-minimal.c). If PT_LOAD p_align is greater than or equal to hostpage size, the GLRO(dl_pagesize) is actually the host pagesize as set in the auxillary vectors. So, there is no explicit mmap request for the remaining target-pages on the last hostpage. The glibc assumes that particular space as available and subsequent attempts to use those addresses lead to crash as the target_mmap has not marked them valid for those target-pages. The issue is seen when trying to chroot to 16.04-x86_64 ubuntu on a PPC64 host where the fork fails to access the thread_id as it is allocated on a page not marked valid. The recent glibc doesn't have checks for thread-id in fork, but the issue can manifest somewhere else, none the less. The fix here is to map all the target-pages of the hostpage during the elfload if the p_align is greater than or equal to hostpage size, for data segment to allow the glibc for proper consumption. Signed-off-by: Shivaprasad G Bhat <sbhat@linux.vnet.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <153553435604.51992.5640085189104207249.stgit@lep8c.aus.stglabs.ibm.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-09-07target-ppc: Extend HWCAP2 bits for ISA 3.0Sandipan Das
This adds the HWCAP2 bit to detect if a linux user process is running on an ISA 3.0 compliant cpu like POWER9. This can be verified using a simple test program that prints the value in the auxiliary vector for AT_HWCAP2 as shown below. Before: $ qemu-ppc64le -cpu power8 test 0x8c000000 $ qemu-ppc64le -cpu power9 test 0x8c000000 After: $ qemu-ppc64le -cpu power8 test 0x8c000000 $ qemu-ppc64le -cpu power9 test 0x8c800000 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-08-24elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS tooAleksandar Markovic
Starting from nanoMIPS introduction, machine variant can be EM_MIPS or EM_NANOMIPS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-07-22linux-user: fix ELF load alignment errorLaurent Vivier
When we try to use some targets on ppc64, it can happen the target doesn't support the host page size to align ELF load sections and fails with: ELF load command alignment not page-aligned Since commit a70daba3771 ("linux-user: Tell guest about big host page sizes") the host page size is used to align ELF sections, but this doesn't work if the alignment required by the load section is smaller than the host one. For these cases, we continue to use the TARGET_PAGE_SIZE instead of the host one. I have tested this change on ppc64, and it fixes qemu linux-user for: s390x, m68k, i386, arm, aarch64, hppa and I have tested it doesn't break the following targets: x86_64, mips64el, sh4 mips and mipsel abort, but I think for another reason. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [lv: fixed "info->alignment = 0"] Message-Id: <20180716195349.29959-1-laurent@vivier.eu>
2018-06-29target/arm: Implement ARMv8.2-DotProdRichard Henderson
We've already added the helpers with an SVE patch, all that remains is to wire up the aa64 and aa32 translators. Enable the feature within -cpu max for CONFIG_USER_ONLY. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-36-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-29target/arm: Enable SVE for aarch64-linux-userRichard Henderson
Enable ARM_FEATURE_SVE for the generic "max" cpu. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-35-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-10target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decodeRichard Henderson
The insns in the ARMv8.1-Atomics are added to the existing load/store exclusive and load/store reg opcode spaces. Rearrange the top-level decoders for these to accomodate. The Atomics insns themselves still generate Unallocated. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-8-richard.henderson@linaro.org [PMM: Drop the ARM_FEATURE_V8_1 feature flag] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-03linux-user: ARM-FDPIC: Add support of FDPIC for ARM.Christophe Lyon
Add FDPIC info into image_info structure since interpreter info is on stack and needs to be saved to be accessed later on. Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180430080404.7323-4-christophe.lyon@st.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-05-03linux-user: ARM-FDPIC: Identify ARM FDPIC binariesChristophe Lyon
Define an ARM-specific version of elf_is_fdpic: FDPIC ELF objects are identified with e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC. Co-Authored-By: Mickaël Guêné <mickael.guene@st.com> Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180430080404.7323-3-christophe.lyon@st.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-05-03Remove CONFIG_USE_FDPIC.Christophe Lyon
We want to avoid code disabled by default, because it ends up less tested. This patch removes all instances of #ifdef CONFIG_USE_FDPIC, most of which can be safely kept. For the ones that should be conditionally executed, we define elf_is_fdpic(). Without this patch, defining CONFIG_USE_FDPIC would prevent QEMU from building precisely because elf_is_fdpic is not defined. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180430080404.7323-2-christophe.lyon@st.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-04-10linux-user: implement HWCAP bits on MIPSJames Cowgill
Add support for the two currently defined HWCAP bits on MIPS - R6 and MSA. Buglink: https://bugs.launchpad.net/qemu/+bug/1754372 Signed-off-by: James Cowgill <james.cowgill@mips.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180315151348.6451-1-james.cowgill@mips.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-03-20linux-user: init_guest_space: Try to make ARM space+commpage continuousLuke Shumaker
At a fixed distance after the usable memory that init_guest_space maps, for 32-bit ARM targets we also need to map a commpage. The normal init_guest_space logic doesn't keep this in mind when searching for an address range. If !host_start, then try to find a big continuous segment where we can put both the usable memory and the commpage; we then munmap that segment and set current_start to that address; and let the normal code mmap the usable memory and the commpage separately. That is: if we don't have hint of where to start looking for memory, come up with one that is better than NULL. Depending on host_size and guest_start, there may or may not be a gap between the usable memory and the commpage, so this is slightly more restrictive than it needs to be; but it's only a hint, so that's OK. We only do that for !host start, because if host_start, then either: - we got an address passed in with -B, in which case we don't want to interfere with what the user said; - or host_start is based off of the ELF image's loaddr. The check "if (host_start && real_start != current_start)" suggests that we really want lowest available address that is >= loaddr. I don't know why that is, but I'm trusting that Paul Brook knew what he was doing when he wrote the original version of that check in c581deda322080e8beb88b2e468d4af54454e4b3 way back in 2010. Signed-off-by: Luke Shumaker <lukeshu@parabola.nu> Message-Id: <20171228180814.9749-11-lukeshu@lukeshu.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-03-17Merge remote-tracking branch 'remotes/xtensa/tags/20180316-xtensa' into stagingPeter Maydell
target/xtensa linux-user support. - small cleanup for xtensa registers dumping (-d cpu); - add support for debugging linux-user process with xtensa-linux-gdb (as opposed to xtensa-elf-gdb), which can only access unprivileged registers; - enable MTTCG for target/xtensa; - cleanup in linux-user/mmap area making sure that it works correctly with limited 30-bit-wide user address space; - import xtensa-specific definitions from the linux kernel, conditionalize user-only/softmmu-only code and add handlers for signals, exceptions, process/thread creation and core registers dumping. # gpg: Signature made Fri 16 Mar 2018 16:46:19 GMT # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180316-xtensa: MAINTAINERS: fix W: address for xtensa qemu-binfmt-conf.sh: add qemu-xtensa target/xtensa: add linux-user support linux-user: drop unused target_msync function linux-user: fix target_mprotect/target_munmap error return values linux-user: fix assertion in shmdt linux-user: fix mmap/munmap/mprotect/mremap/shmat target/xtensa: support MTTCG target/xtensa: use correct number of registers in gdbstub target/xtensa: mark register windows in the dump target/xtensa: dump correct physical registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # linux-user/syscall.c
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