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2024-02-12Merge tag 'pull-maintainer-updates-090224-1' of ↵Peter Maydell
https://gitlab.com/stsquad/qemu into staging testing, doc and gdbstub updates: - add sqlite3 to openSUSE image - mark CRIS as deprecated - re-enable the TCG plugin tests - use select for semihosting - implement syscall catching in gdbstub # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmXGZtQACgkQ+9DbCVqe # KkTegAgAg7Kkd0Pa2cgkPfNPYR5yT4hYurjVSfi/69cOpj/Vadsav4WWFsuUiQMI # FfKWCNDo5lmNcWIPKgC0oeWVwxal4IhqhO8f9lRIYqg9z4bRkZbdsrvh8J52Q6Xh # Bu9UAEk5KBGrMfEdsAwHnVDg435c7IGdJZnE/iKBK1aKljS5LOiX1J6ZxrqUoMsJ # keTAcdXyvs/BIz68c87AHrW/HKO9KKLgHA2n7T/l2N5KJdoa3p8La9py+v1SGUh8 # 6JlDRYR1H16mITS8tm6ZffPqcOpfHXp7DRquu7obVS5+CVTJ2H9w8TICw56rqMg7 # cVnysNLhdS18cMNKD2Jx3zgd5Nq/cg== # =deHm # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 Feb 2024 17:54:28 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * tag 'pull-maintainer-updates-090224-1' of https://gitlab.com/stsquad/qemu: tests/tcg: Add the syscall catchpoint gdbstub test gdbstub: Implement catching syscalls gdbstub: Add syscall entry/return hooks gdbstub: Allow specifying a reason in stop packets gdbstub: Expose TARGET_SIGTRAP in a target-agnostic way kconfig: use "select" to enable semihosting Revert "hw/elf_ops: Ignore loadable segments with zero size" configure: run plugin TCG tests again docs: mark CRIS support as deprecated tests/docker: Add sqlite3 module to openSUSE Leap container Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-12Merge tag 'misc-fixes-pull-request' of https://gitlab.com/berrange/qemu into ↵Peter Maydell
staging - LUKS support for detached headers - Update x86 CPU model docs and script - Add missing close of chardev QIOChannel - More trace events o nTKS handshake - Drop unsafe VNC constants - Increase NOFILE limit during startup # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2vOm/bJrYpEtDo4/vobrtBUQT98FAmXGMNUACgkQvobrtBUQ # T998JQ//SqQ3L/AZmhE5cIwZ1XipSMMZ/yEoVIyniA3tL41S7Oimj3O9XvY68TEG # nnj9Oh+zOlVLxauTHAczveJ7z+XfonQZS3HrbGRUTHU+ezGVjyM618e/h9pSQtYI # +CCkrjtey1NoT42/um4D/bKg/B2XQeulS+pD12Z9l5zbqEZiw0R9+UwVIJ52G811 # 5UQgIjJ7GNFzalxqiMCkGc0nTyU8keEXQJcdZ4droo42DnU4pZeQWGDimzP61JnW # 1Crm6aZSuUriUbVmxJde+2eEdPSR4rr/yQ4Pw06hoi1QJALSgGYtOTo8+qsyumHd # us/2ouMrxOMdsIk4ViAkSTiaje9agPj84VE1Z229Y/uqZcEAuX572n730/kkzqUv # ZDKxMz0v3rzpkjFmsgj5D4yqJaQp4zn1zYm98ld7HWJVIOf3GSvpaNg9J6jwN7Gi # HKKkvYns9pxg3OSx++gqnM32HV6nnMDFiddipl/hTiUsnNlnWyTDSvJoNxIUU5+l # /uEbbdt8xnxx1JP0LiOhgmz6N6FU7oOpaPuJ5CD8xO2RO8D1uBRvmpFcdOTDAfv0 # uYdjhKBI+quKjE64p7gNWYCoqZtipRIJ6AY2VaPU8XHx8GvGFwBLX64oLYiYtrBG # gkv3NTHRkMhQw9cGQcZIgZ+OLU+1eNF+m9EV7LUjuKl0HWC3Vjs= # =61zI # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 Feb 2024 14:04:05 GMT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * tag 'misc-fixes-pull-request' of https://gitlab.com/berrange/qemu: tests: Add case for LUKS volume with detached header crypto: Introduce 'detached-header' field in QCryptoBlockInfoLUKS block: Support detached LUKS header creation using qemu-img block: Support detached LUKS header creation using blockdev-create crypto: Modify the qcrypto_block_create to support creation flags qapi: Make parameter 'file' optional for BlockdevCreateOptionsLUKS crypto: Support LUKS volume with detached header io: add trace event when cancelling TLS handshake chardev: close QIOChannel before unref'ing docs: re-generate x86_64 ABI compatibility CSV docs: fix highlighting of CPU ABI header rows scripts: drop comment about autogenerated CPU API file softmmu: remove obsolete comment about libvirt timeouts ui: drop VNC feature _MASK constants qemu_init: increase NOFILE soft limit on POSIX crypto: Introduce SM4 symmetric cipher algorithm meson: sort C warning flags alphabetically Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-12qapi: Move @String out of common.json to discourage reuseMarkus Armbruster
Use of String is problematic, because it results in awkward interface documentation. The previous commit cleaned up one instance. Move String out of common.json next to its remaining users in net.json to discourage reuse elsewhere. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240205074709.3613229-15-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2024-02-12qapi: Improve documentation of file descriptor socket addressesMarkus Armbruster
SocketAddress branch @fd is documented in enum SocketAddressType, unlike the other branches. That's because the branch's type is String from common.json. Use a local copy of String, so we can put the documentation in the usual place. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240205074709.3613229-14-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2024-02-11lasi: Add reset I/O ports for LASI audio and FDCHelge Deller
Linux writes zeroes at bootup into the default ports for LASI audio and LASI floppy controller to reset those devices. Allow writing to those registers to avoid HPMCs. Signed-off-by: Helge Deller <deller@gmx.de>
2024-02-11hw/pci-host/astro: Implement Hard Fail and Soft Fail modeHelge Deller
The Astro/Elroy chip can work in either Hard-Fail or Soft-Fail mode. Hard fail means the system bus will send an HPMC (=crash) to the processor, soft fail means the system bus will ignore timeouts of MMIO-reads or MMIO-writes and return -1ULL. The HF mode is controlled by a bit in the status register and is usually programmed by the OS. Return the corresponing values based on the current value of that bit. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-09gdbstub: Add syscall entry/return hooksIlya Leoshkevich
The upcoming syscall catchpoint support needs to get control on syscall entry and return. Provide the necessary hooks for that, which are no-ops for now. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240202152506.279476-4-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240207163812.3231697-13-alex.bennee@linaro.org>
2024-02-09gdbstub: Allow specifying a reason in stop packetsIlya Leoshkevich
The upcoming syscall catchpoint support needs to send stop packets with an associated reason to GDB. Add an extra parameter to gdb_handlesig() for that, and rename it to gdb_handlesig_reason(). Provide a compatibility wrapper with an old name. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240202152506.279476-3-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240207163812.3231697-12-alex.bennee@linaro.org>
2024-02-09Revert "hw/elf_ops: Ignore loadable segments with zero size"Alex Bennée
This regressed qemu-system-xtensa: TEST test_load_store on xtensa qemu-system-xtensa: Some ROM regions are overlapping These ROM regions might have been loaded by direct user request or by default. They could be BIOS/firmware images, a guest kernel, initrd or some other file loaded into guest memory. Check whether you intended to load all this guest code, and whether it has been built to load to the correct addresses. The following two regions overlap (in the memory address space): test_load_store ELF program header segment 1 (addresses 0x0000000000001000 - 0x0000000000001f26) test_load_store ELF program header segment 2 (addresses 0x0000000000001ab8 - 0x0000000000001ab8) make[1]: *** [Makefile:187: run-test_load_store] Error 1 This reverts commit 62570f1434160d356311e1c217537e24a4ac85cd. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240207163812.3231697-5-alex.bennee@linaro.org>
2024-02-09Merge tag 'pull-riscv-to-apply-20240209' of ↵Peter Maydell
https://github.com/alistair23/qemu into staging RISC-V PR for 9.0 * Check for 'A' extension on all atomic instructions * Add support for 'B' extension * Internally deprecate riscv_cpu_options * Implement optional CSR mcontext of debug Sdtrig extension * Internally add cpu->cfg.vlenb and remove cpu->cfg.vlen * Support vlenb and vregs[] in KVM * RISC-V gdbstub and TCG plugin improvements * Remove vxrm and vxsat from FCSR * Use RISCVException as return type for all csr ops * Use g_autofree more and fix a memory leak * Add support for Zaamo and Zalrsc * Support new isa extension detection devicetree properties * SMBIOS support for RISC-V virt machine * Enable xtheadsync under user mode * Add rv32i,rv32e and rv64e CPUs # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmXGBRAACgkQr3yVEwxT # gBPqVA//etMiwP8+lQb2E4pw+QwBIzpm3qFyBlqgSCFrekj1u2kYNd4CH3CKurWE # ysoQ6OAMeb0MUbRHdjrejjzD/wOg7JNA9h7ynM1VbupveBrJY3GWC6qQWSG+A1j/ # LSgmr/dDya74chDxjxa+7ld3xqloHi5OtdGaeORfdPXl7mjCCKKCoSKYCex1ykup # uuB7bsjeWeWEbuUsntmeuHJLZJuhpnbuZJmp17tEo+3vWXqjxV00Lik+XMwh3gua # KOLiAqHjGr2NEhA3Mg1JLcQ+6JLTDM9ugZpQeNGQwMkfuB/RAU7jO/1Di3flbadF # 8l2xOHu3mydDbfdxTGZNJjcIrMTX/YEewAYZLRYpNsyPOMntgq8HEegwCdWGvK7C # M5Tc59MNSuBt+zkZkHd21qLYusa2ThP4YT/schh7IA+2F1TSKdhlptEzi2oebIc7 # ilLSgZ9Of72QlAH2OPJNSAL9Nbc06MHEM0JiHIJa5u+XdcVRhZus5h1YIOKXisqF # YPP22RnI5Jj5d5csa/0ONAZGFh5SRMTJtpjKoKSkzoYJWDjCQ2MiUAOmLscchMZd # wbK0vjeRf6kRG4U4z7nTmHS9kzH8RXUZDecVcOITuMpKih9LhUiCZ+xPunFYPycJ # WNFa9/pENcCXJweXvtk4NHwx933rX56678lF6KY2hwUwwaiBOv4= # =yuRM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 09 Feb 2024 10:57:20 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20240209' of https://github.com/alistair23/qemu: (61 commits) target/riscv: add rv32i, rv32e and rv64e CPUs target/riscv/cpu.c: add riscv_bare_cpu_init() target/riscv: Enable xtheadsync under user mode qemu-options: enable -smbios option on RISC-V target/riscv: SMBIOS support for RISC-V virt machine smbios: function to set default processor family smbios: add processor-family option target/riscv: support new isa extension detection devicetree properties target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS target/riscv: Expose Zaamo and Zalrsc extensions target/riscv: Check 'A' and split extensions for atomic instructions target/riscv: Add Zaamo and Zalrsc extension infrastructure hw/riscv/virt.c: use g_autofree in create_fdt_* hw/riscv/virt.c: use g_autofree in virt_machine_init() hw/riscv/virt.c: use g_autofree in create_fdt_virtio() hw/riscv/virt.c: use g_autofree in create_fdt_sockets() hw/riscv/virt.c: use g_autofree in create_fdt_socket_cpus() hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix() hw/riscv/virt-acpi-build.c: fix leak in build_rhct() target/riscv: Use RISCVException as return type for all csr ops ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-09crypto: Modify the qcrypto_block_create to support creation flagsHyman Huang
Expand the signature of qcrypto_block_create to enable the formation of LUKS volumes with detachable headers. To accomplish that, introduce QCryptoBlockCreateFlags to instruct the creation process to set the payload_offset_sector to 0. Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-02-09crypto: Support LUKS volume with detached headerHyman Huang
By enhancing the LUKS driver, it is possible to implement the LUKS volume with a detached header. Normally a LUKS volume has a layout: disk: | header | key material | disk payload data | With a detached LUKS header, you need 2 disks so getting: disk1: | header | key material | disk2: | disk payload data | There are a variety of benefits to doing this: * Secrecy - the disk2 cannot be identified as containing LUKS volume since there's no header * Control - if access to the disk1 is restricted, then even if someone has access to disk2 they can't unlock it. Might be useful if you have disks on NFS but want to restrict which host can launch a VM instance from it, by dynamically providing access to the header to a designated host * Flexibility - your application data volume may be a given size and it is inconvenient to resize it to add encryption.You can store the LUKS header separately and use the existing storage volume for payload * Recovery - corruption of a bit in the header may make the entire payload inaccessible. It might be convenient to take backups of the header. If your primary disk header becomes corrupt, you can unlock the data still by pointing to the backup detached header Take the raw-format image as an example to introduce the usage of the LUKS volume with a detached header: 1. prepare detached LUKS header images $ dd if=/dev/zero of=test-header.img bs=1M count=32 $ dd if=/dev/zero of=test-payload.img bs=1M count=1000 $ cryptsetup luksFormat --header test-header.img test-payload.img > --force-password --type luks1 2. block-add a protocol blockdev node of payload image $ virsh qemu-monitor-command vm '{"execute":"blockdev-add", > "arguments":{"node-name":"libvirt-1-storage", "driver":"file", > "filename":"test-payload.img"}}' 3. block-add a protocol blockdev node of LUKS header as above. $ virsh qemu-monitor-command vm '{"execute":"blockdev-add", > "arguments":{"node-name":"libvirt-2-storage", "driver":"file", > "filename": "test-header.img" }}' 4. object-add the secret for decrypting the cipher stored in LUKS header above $ virsh qemu-monitor-command vm '{"execute":"object-add", > "arguments":{"qom-type":"secret", "id": > "libvirt-2-storage-secret0", "data":"abc123"}}' 5. block-add the raw-drived blockdev format node $ virsh qemu-monitor-command vm '{"execute":"blockdev-add", > "arguments":{"node-name":"libvirt-1-format", "driver":"raw", > "file":"libvirt-1-storage"}}' 6. block-add the luks-drived blockdev to link the raw disk with the LUKS header by specifying the field "header" $ virsh qemu-monitor-command vm '{"execute":"blockdev-add", > "arguments":{"node-name":"libvirt-2-format", "driver":"luks", > "file":"libvirt-1-format", "header":"libvirt-2-storage", > "key-secret":"libvirt-2-format-secret0"}}' 7. hot-plug the virtio-blk device finally $ virsh qemu-monitor-command vm '{"execute":"device_add", > "arguments": {"num-queues":"1", "driver":"virtio-blk-pci", > "drive": "libvirt-2-format", "id":"virtio-disk2"}}' Starting a VM with a LUKS volume with detached header is somewhat similar to hot-plug in that both maintaining the same json command while the starting VM changes the "blockdev-add/device_add" parameters to "blockdev/device". Signed-off-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-02-09qemu_init: increase NOFILE soft limit on POSIXFiona Ebner
In many configurations, e.g. multiple vNICs with multiple queues or with many Ceph OSDs, the default soft limit of 1024 is not enough. QEMU is supposed to work fine with file descriptors >= 1024 and does not use select() on POSIX. Bump the soft limit to the allowed hard limit to avoid issues with the aforementioned configurations. Of course the limit could be raised from the outside, but the man page of systemd.exec states about 'LimitNOFILE=': > Don't use. > [...] > Typically applications should increase their soft limit to the hard > limit on their own, if they are OK with working with file > descriptors above 1023, If the soft limit is already the same as the hard limit, avoid the superfluous setrlimit call. This can avoid a warning with a strict seccomp filter blocking setrlimit if NOFILE was already raised before executing QEMU. Buglink: https://bugzilla.proxmox.com/show_bug.cgi?id=4507 Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Fiona Ebner <f.ebner@proxmox.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2024-02-09Merge tag 'migration-staging-pull-request' of https://gitlab.com/peterx/qemu ↵Peter Maydell
into staging Migration pull - William's fix on hwpoison migration which used to crash QEMU - Peter's multifd cleanup + bugfix + optimizations - Avihai's fix on multifd crash over non-socket channels - Fabiano's multifd thread-race fix - Peter's CI fix series # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZcREtRIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wacrwEAl2aeQkh51h/e+OKX7MG4/4Y6Edf6Oz7o # IJLk/cyrUFQA/2exo2lOdv5zHNOJKwAYj8HYDraezrC/MK1eED4Wji0M # =k53l # -----END PGP SIGNATURE----- # gpg: Signature made Thu 08 Feb 2024 03:04:21 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal] # gpg: aka "Peter Xu <peterx@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-staging-pull-request' of https://gitlab.com/peterx/qemu: (34 commits) ci: Update comment for migration-compat-aarch64 ci: Remove tag dependency for build-previous-qemu tests/migration-test: Stick with gicv3 in aarch64 test migration/multifd: Add a synchronization point for channel creation migration/multifd: Unify multifd and TLS connection paths migration/multifd: Move multifd_send_setup into migration thread migration/multifd: Move multifd_send_setup error handling in to the function migration/multifd: Remove p->running migration/multifd: Join the TLS thread migration: Fix logic of channels and transport compatibility check migration/multifd: Optimize sender side to be lockless migration/multifd: Fix MultiFDSendParams.packet_num race migration/multifd: Stick with send/recv on function names migration/multifd: Cleanup multifd_load_cleanup() migration/multifd: Cleanup multifd_save_cleanup() migration/multifd: Rewrite multifd_queue_page() migration/multifd: Change retval of multifd_send_pages() migration/multifd: Change retval of multifd_queue_page() migration/multifd: Split multifd_send_terminate_threads() migration/multifd: Forbid spurious wakeups ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-09smbios: function to set default processor familyHeinrich Schuchardt
Provide a function to set the default processor family. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20240123184229.10415-3-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-08Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingPeter Maydell
Block layer patches - Allow concurrent BB context changes - virtio: Re-enable notifications after drain - virtio-blk: Fix missing use of irqfd - scsi: Don't ignore most usb-storage properties - blkio: Respect memory-alignment for bounce buffer allocations - iotests tmpdir fixes - virtio-blk: Code cleanups # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmXEkwgRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9Y3jA//TmSBVqHljauyImYOgCt8qCXACttV0xhQ # Q5ldUNx/JmIFMoUR7OlpVAL2MtvdwE0jjY+sDlEmWtz4IFJcCsCTUCHZZb8blreb # +mnMkqrQ6Nb3tPR2jeIknrXqNy1ffyjZItktjWXVcl6jaHB8YabHHqszs9DIaf4n # lcKovBKxula8ckMgvm48wCwTtS7VEPeuC5FrOqUqTtuhg+QKp5ZVoyVFHtf6GKTD # iuXzCd4yxu4fDKAthJJj4N1bQaOmCKU7K9N/665wj9P2TyfmwlBAfNwNAlYbdX1E # Sv7eSioQs2+oUxmfD/PUsF7wTYtDCrSAUFn1kP/XdRyXPJR3dHGiBKV9w9CaWNrU # y8rqOhxVcuoBLRljTF32BK4HniAREjRngtpT2FnQQIyedZrXIwyTAWjs+LW12T6O # NMiU603Nl9ZYhO1et2+qspsVpNIfEpQWpK+OCon6E+ggj1ea+pfqU30VPx4JU05I # VLiydluIbehSkRlTHgFcTgApmx843OGW7CvWfRyen86Cexgx3DEjJUQ4/bYqaCha # yLIi91rToSDmtlzJrg9eYiMs5Y6vz+ORvvX5im1RlbUUb7Kx/LaA4BU/uArEbBt8 # xXm/grO4hFUGqtLgd2LIjWaHSsLoW4jKeEiExFUUfvH5DG9Zl5HmzFwu+DYxX+im # MJLLetDJAWI= # =8tc0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 08 Feb 2024 08:38:32 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: virtio-blk: avoid using ioeventfd state in irqfd conditional virtio-blk: Use ioeventfd_attach in start_ioeventfd virtio: Re-enable notifications after drain virtio-scsi: Attach event vq notifier with no_poll blkio: Respect memory-alignment for bounce buffer allocations scsi: Don't ignore most usb-storage properties virtio-blk: do not use C99 mixed declarations iotests: give tempdir an identifying name iotests: fix leak of tmpdir in dry-run mode scsi: Await request purging block-backend: Allow concurrent context changes monitor: use aio_co_reschedule_self() virtio-blk: declare VirtIOBlock::rq with a type virtio-blk: add vq_rq[] bounds check in virtio_blk_dma_restart_cb() virtio-blk: clarify that there is at least 1 virtqueue virtio-blk: enforce iothread-vq-mapping validation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-08Merge tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
tcg: Introduce TCG_COND_TST{EQ,NE} target/alpha: Use TCG_COND_TST{EQ,NE} target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} target/s390x: Improve general case of disas_jcc # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmXBpTAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p6gf9HAasTSRECk2cvjW9 # /mcJy0AIaespnI50fG8fm48OoFl0847CdrsJycpZ1spw3W3Wb0cVbMbq/teNMjXZ # 0SGQJFk9Baq7wMhW7VzhSzJ96pcorpQprp7XBMdheLXqpT4zsM/EuwEAepBk8RUG # 3kCeo38dswXE681ZafZkd/8pPzII19sQK8eiMpceeYkBsbbep+DDcnE18Ee4kISS # u0SbuslKVahxd86LKuzrcz0pNFcmFuR5jRP9hmbQ0MfeAn0Pxlndi+ayZNghfgPf # 3hDjskiionFwxb/OoRj45BssTWfDiluWl7IUsHfegPXCQ2Y+woT5Vq6TVGZn0GqS # c6RLQQ== # =TMiE # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 Feb 2024 03:19:12 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240205-2' of https://gitlab.com/rth7680/qemu: (39 commits) tcg/tci: Support TCG_COND_TST{EQ,NE} tcg/s390x: Support TCG_COND_TST{EQ,NE} tcg/s390x: Add TCG_CT_CONST_CMP tcg/s390x: Split constraint A into J+U tcg/ppc: Support TCG_COND_TST{EQ,NE} tcg/ppc: Add TCG_CT_CONST_CMP tcg/ppc: Tidy up tcg_target_const_match tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc tcg/sparc64: Support TCG_COND_TST{EQ,NE} tcg/sparc64: Pass TCGCond to tcg_out_cmp tcg/sparc64: Hoist read of tcg_cond_to_rcond tcg/i386: Use TEST r,r to test 8/16/32 bits tcg/i386: Improve TSTNE/TESTEQ vs powers of two tcg/i386: Support TCG_COND_TST{EQ,NE} tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp tcg/i386: Pass x86 condition codes to tcg_out_cmov tcg/arm: Support TCG_COND_TST{EQ,NE} tcg/arm: Split out tcg_out_cmp() tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-07virtio: Re-enable notifications after drainHanna Czenczek
During drain, we do not care about virtqueue notifications, which is why we remove the handlers on it. When removing those handlers, whether vq notifications are enabled or not depends on whether we were in polling mode or not; if not, they are enabled (by default); if so, they have been disabled by the io_poll_start callback. Because we do not care about those notifications after removing the handlers, this is fine. However, we have to explicitly ensure they are enabled when re-attaching the handlers, so we will resume receiving notifications. We do this in virtio_queue_aio_attach_host_notifier*(). If such a function is called while we are in a polling section, attaching the notifiers will then invoke the io_poll_start callback, re-disabling notifications. Because we will always miss virtqueue updates in the drained section, we also need to poll the virtqueue once after attaching the notifiers. Buglink: https://issues.redhat.com/browse/RHEL-3934 Signed-off-by: Hanna Czenczek <hreitz@redhat.com> Message-ID: <20240202153158.788922-3-hreitz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2024-02-07scsi: Don't ignore most usb-storage propertiesKevin Wolf
usb-storage is for the most part just a wrapper around an internally created scsi-disk device. It uses DEFINE_BLOCK_PROPERTIES() to offer all of the usual block device properties to the user, but then only forwards a few select properties to the internal device while the rest is silently ignored. This changes scsi_bus_legacy_add_drive() to accept a whole BlockConf instead of some individual values inside of it so that usb-storage can now pass the whole configuration to the internal scsi-disk. This enables the remaining block device properties, e.g. logical/physical_block_size or discard_granularity. Buglink: https://issues.redhat.com/browse/RHEL-22375 Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20240131130607.24117-1-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2024-02-07virtio-blk: declare VirtIOBlock::rq with a typeStefan Hajnoczi
The VirtIOBlock::rq field has had the type void * since its introduction in commit 869a5c6df19a ("Stop VM on error in virtio-blk. (Gleb Natapov)"). Perhaps this was done to avoid the forward declaration of VirtIOBlockReq. Hanna Czenczek <hreitz@redhat.com> pointed out the missing type. Specify the actual type because there is no need to use void * here. Suggested-by: Hanna Czenczek <hreitz@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Hanna Czenczek <hreitz@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-ID: <20240206190610.107963-5-stefanha@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2024-02-06oslib-posix: initialize backend memory objects in parallelMark Kanda
QEMU initializes preallocated backend memory as the objects are parsed from the command line. This is not optimal in some cases (e.g. memory spanning multiple NUMA nodes) because the memory objects are initialized in series. Allow the initialization to occur in parallel (asynchronously). In order to ensure optimal thread placement, asynchronous initialization requires prealloc context threads to be in use. Signed-off-by: Mark Kanda <mark.kanda@oracle.com> Message-ID: <20240131165327.3154970-2-mark.kanda@oracle.com> Tested-by: Mario Casquero <mcasquer@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-02-05migration: prevent migration when VM has poisoned memoryWilliam Roche
A memory page poisoned from the hypervisor level is no longer readable. The migration of a VM will crash Qemu when it tries to read the memory address space and stumbles on the poisoned page with a similar stack trace: Program terminated with signal SIGBUS, Bus error. #0 _mm256_loadu_si256 #1 buffer_zero_avx2 #2 select_accel_fn #3 buffer_is_zero #4 save_zero_page #5 ram_save_target_page_legacy #6 ram_save_host_page #7 ram_find_and_save_block #8 ram_save_iterate #9 qemu_savevm_state_iterate #10 migration_iteration_run #11 migration_thread #12 qemu_thread_start To avoid this VM crash during the migration, prevent the migration when a known hardware poison exists on the VM. Signed-off-by: William Roche <william.roche@oracle.com> Link: https://lore.kernel.org/r/20240130190640.139364-2-william.roche@oracle.com Signed-off-by: Peter Xu <peterx@redhat.com>
2024-02-03tcg: Introduce TCG_COND_TST{EQ,NE}Richard Henderson
Add the enumerators, adjust the helpers to match, and dump. Not supported anywhere else just yet. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03Merge tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
tests/tcg: Fix multiarch/gdbstub/prot-none.py hw/core: Convert cpu_mmu_index to a CPUClass hook tcg/loongarch64: Set vector registers call clobbered target/sparc: floating-point cleanup linux-user/aarch64: Add padding before __kernel_rt_sigreturn # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW95WkdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p+Qf/eVmh5q0pZqcur7ft # 8FO0wlIz55OfhaA9MIpH7LEIHRKY37Ybebw2K6SPnx4FmPhLkaj4KXPPjT2nzdXw # J2nQM+TOyxOd18GG8P80qFQ1a72dj8VSIRVAl9T46KuPXS5B7luArImfBlUk/GwV # Qr/XkOPwVTp05E/ccMJ8PMlcVZw9osHVLqsaFVbsUv/FylTmstzA9c5Gw7/FTfkG # T2rk+7go+F4IXs/9uQuuFMOpQOZngXE621hnro+qle7j9oarEUVJloAgVn06o59O # fUjuoKO0aMCr2iQqNJTH7Dnqp5OIzzxUoXiNTOj0EimwWfAcUKthoFO2LGcy1/ew # wWNR/Q== # =e3J3 # -----END PGP SIGNATURE----- # gpg: Signature made Sat 03 Feb 2024 07:04:09 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu: (58 commits) linux-user/aarch64: Add padding before __kernel_rt_sigreturn target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK target/sparc: Split fcc out of env->fsr target/sparc: Remove cpu_fsr target/sparc: Split cexc and ftt from env->fsr target/sparc: Merge check_ieee_exceptions with FPop helpers target/sparc: Clear cexc and ftt in do_check_ieee_exceptions target/sparc: Split ver from env->fsr target/sparc: Introduce cpu_get_fsr, cpu_put_fsr target/sparc: Remove qt0, qt1 temporaries target/sparc: Use i128 for Fdmulq target/sparc: Use i128 for FdTOq, FxTOq target/sparc: Use i128 for FsTOq, FiTOq target/sparc: Use i128 for FCMPq, FCMPEq target/sparc: Use i128 for FqTOd, FqTOx target/sparc: Use i128 for FqTOs, FqTOi target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq target/sparc: Use i128 for FSQRTq target/sparc: Inline FNEG, FABS target/sparc: Introduce gen_{load,store}_fpr_Q ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-03include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03include/exec: Implement cpu_mmu_index genericallyRichard Henderson
For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-03include/hw/core: Add mmu_index to CPUClassRichard Henderson
To be used after all targets have populated the hook. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-02Merge tag 'pull-target-arm-20240202' of ↵Peter Maydell
https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02net: make nb_nics and nd_table[] static in net/net.cDavid Woodhouse
Also remove the stale declaration of host_net_devices; the actual definition was removed long ago in commit 7cc28cb06104 ("net: Remove the deprecated 'host_net_add' and 'host_net_remove' HMP commands") Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02net: remove qemu_show_nic_models(), qemu_find_nic_model()David Woodhouse
These old functions can be removed now too. Let net_param_nic() print the full set of network devices directly, and also make it note that a list more specific to this platform/config will be available by using '-nic model=help' instead. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/pci: remove pci_nic_init_nofail()David Woodhouse
This function is no longer used, as all its callers have been converted to use pci_init_nic_devices() instead. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02net: remove qemu_check_nic_model()David Woodhouse
There are no callers of this function any more, as they have all been converted to qemu_{create,configure}_nic_device(). Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/lasi_i82596: use qemu_create_nic_device()David Woodhouse
Create the device only if there is a corresponding NIC config for it. Remove the explicit check on nd_table[0].used from hw/hppa/machine.c which (since commit d8a3220005d7) tries to do the same thing. The lasi_82596 support has been disabled since it was first introduced, since enable_lasi_lan() has always been zero. This allows the user to enable it by explicitly requesting a NIC model 'lasi_82596' or just using the alias 'lasi'. Otherwise, it defaults to a PCI NIC as before. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/etraxfs-eth: use qemu_configure_nic_device()David Woodhouse
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/lan9118: use qemu_configure_nic_device()David Woodhouse
Some callers instantiate the device unconditionally, others will do so only if there is a NICInfo to go with it. This appears to be fairly random, but preseve the existing behaviour for now. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/smc91c111: use qemu_configure_nic_device()David Woodhouse
Some callers instantiate the device unconditionally, others will do so only if there is a NICInfo to go with it. This appears to be fairly random, but preserve the existing behaviour of each caller for now. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/xen: use qemu_create_nic_bus_devices() to instantiate Xen NICsDavid Woodhouse
When instantiating XenBus itself, for each NIC which is configured with either the model unspecified, or set to to "xen" or "xen-net-device", create a corresponding xen-net-device for it. Now we can revert the previous more hackish version which relied on the platform code explicitly registering the NICs on its own XenBus, having returned the BusState* from xen_bus_init() itself. This also fixes the setup for Xen PV guests, which was previously broken in various ways and never actually managed to peer with the netdev. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2024-02-02hw/i386/pc: use qemu_get_nic_info() and pci_init_nic_devices()David Woodhouse
Eliminate direct access to nd_table[] and nb_nics by processing the the Xen and ISA NICs first and then calling pci_init_nic_devices() for the rest. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2024-02-02hw/pci: add pci_init_nic_devices(), pci_init_nic_in_slot()David Woodhouse
The loop over nd_table[] to add PCI NICs is repeated in quite a few places. Add a helper function to do it. Some platforms also try to instantiate a specific model in a specific slot, to match the real hardware. Add pci_init_nic_in_slot() for that purpose. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2024-02-02net: add qemu_create_nic_bus_devices()David Woodhouse
This will instantiate any NICs which live on a given bus type. Each bus is allowed *one* substitution (for PCI it's virtio → virtio-net-pci, for Xen it's xen → xen-net-device; no point in overengineering it unless we actually want more). Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02net: add qemu_{configure,create}_nic_device(), qemu_find_nic_info()David Woodhouse
Most code which directly accesses nd_table[] and nb_nics uses them for one of two things. Either "I have created a NIC device and I'd like a configuration for it", or "I will create a NIC device *if* there is a configuration for it". With some variants on the theme around whether they actually *check* if the model specified in the configuration is the right one. Provide functions which perform both of those, allowing platforms to be a little more consistent and as a step towards making nd_table[] and nb_nics private to the net code. One might argue that platforms ought to be consistent about whether they create the unconfigured devices or not, but making significant user-visible changes is explicitly *not* the intent right now. The new functions leave the 'model' field of the NICInfo as NULL after using it for the default NIC model, unlike the qemu_check_nic_model() function which does set nd->model to match default_model explicitly. This is acceptable because there is no code which consumes nd->model except this NIC-matching code in net/net.c, and no reasonable excuse for any code wanting to use nd->model in future. Also export the qemu_find_nic_info() helper, as some platforms have special cases they need to handle. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/arm: Connect SPI Controller to BCM2835Rayhan Faizel
This patch will allow the SPI controller to be accessible from BCM2835 based boards as SPI0. SPI driver is usually disabled by default and config.txt does not work. Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-3-rayhan.faizel@gmail.com [PMM: indent tweak] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/ssi: Implement BCM2835 SPI ControllerRayhan Faizel
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/arm: Add GMAC devices to NPCM7XX SoCHao Wu
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-3-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/net: Add NPCMXXX GMAC deviceHao Wu
This patch implements the basic registers of GMAC device and sets registers for networking functionalities. Squashed IRQ Implementation patch into this one for compliation. Tested: The following message shows up with the change: Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E] (mii_bus:phy_addr=stmmac-0:00, irq=POLL) stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx Change-Id: If71c6d486b95edcccba109ba454870714d7e0940 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-2-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]Philippe Mathieu-Daudé
The M2Sxxx SoC family can only be used with Cortex-M3. Propagating the CPU type from the board level is pointless. Hard-code the CPU type at the SoC level. Remove the now ignored MachineClass::default_cpu_type field. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/core: Remove transitional infrastructure from BusClassPeter Maydell
BusClass currently has transitional infrastructure to support subclasses which implement the legacy BusClass::reset method rather than the Resettable interface. We have now removed all the users of BusClass::reset in the tree, so we can remove the transitional infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-6-peter.maydell@linaro.org
2024-02-01Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into ↵Peter Maydell
staging aspeed queue: * Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 # 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD # lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q # 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb # 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj # wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI # yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo # ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH # 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ # 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ # 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb # D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= # =0C5S # -----END PGP SIGNATURE----- # gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu: hw/fsi: Update MAINTAINER list hw/fsi: Added FSI documentation hw/fsi: Added qtest hw/arm: Hook up FSI module in AST2600 hw/fsi: Aspeed APB2OPB & On-chip peripheral bus hw/fsi: Introduce IBM's FSI master hw/fsi: Introduce IBM's cfam hw/fsi: Introduce IBM's fsi-slave model hw/fsi: Introduce IBM's FSI Bus hw/fsi: Introduce IBM's scratchpad device hw/fsi: Introduce IBM's Local bus hw/arm/aspeed: Check for CPU types in machine_run_board_init() hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper hw/arm/aspeed: Init CPU defaults in a common helper hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() hw/arm/aspeed: Remove dead code tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-01hw/arm: Hook up FSI module in AST2600Ninad Palsule
This patchset introduces IBM's Flexible Service Interface(FSI). Time for some fun with inter-processor buses. FSI allows a service processor access to the internal buses of a host POWER processor to perform configuration or debugging. FSI has long existed in POWER processes and so comes with some baggage, including how it has been integrated into the ASPEED SoC. Working backwards from the POWER processor, the fundamental pieces of interest for the implementation are: 1. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on buses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block. 2. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached. 3. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM. 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The implementation appears as following in the qemu device tree: (qemu) info qtree bus: main-system-bus type System ... dev: aspeed.apb2opb, id "" gpio-out "sysbus-irq" 1 mmio 000000001e79b000/0000000000001000 bus: opb.1 type opb dev: fsi.master, id "" bus: fsi.bus.1 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: fsi.lbus.1 type lbus dev: scratchpad, id "" address = 0 (0x0) bus: opb.0 type opb dev: fsi.master, id "" bus: fsi.bus.0 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: fsi.lbus.0 type lbus dev: scratchpad, id "" address = 0 (0x0) The LBUS is modelled to maintain the qdev bus hierarchy and to take advantage of the object model to automatically generate the CFAM configuration block. The configuration block presents engines in the order they are attached to the CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the 'config' member of LBusDeviceClass to match the engine's type. CFAM designs offer a lot of flexibility, for instance it is possible for a CFAM to be simultaneously driven from multiple FSI links. The modeling is not so complete; it's assumed that each CFAM is attached to a single FSI slave (as a consequence the CFAM subclasses the FSI slave). As for FSI, its symbols and wire-protocol are not modelled at all. This is not necessary to get FSI off the ground thanks to the mapping of the CFAM address space onto the OPB address space - the models follow this directly and map the CFAM memory region into the OPB's memory region. Future work includes supporting more advanced accesses that drive the FSI master directly rather than indirectly via the CFAM mapping, which will require implementing the FSI state machine and methods for each of the FSI symbols on the slave. Further down the track we can also look at supporting the bitbanged SoftFSI drivers in Linux by extending the FSI slave model to resolve sequences of GPIO IRQs into FSI symbols, and calling the associated symbol method on the slave to map the access onto the CFAM. Testing: Tested by reading cfam config address 0 on rainier machine type. root@p10bmc:~# pdbg -a getcfam 0x0 p0: 0x0 = 0xc0022d15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Aspeed APB2OPB & On-chip peripheral busNinad Palsule
This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved FSIMasterState under AspeedAPB2OPBState - modified fsi_opb_fsi_master_address() and fsi_opb_opb2fsi_address() - instroduced fsi_aspeed_apb2opb_init() - reworked fsi_aspeed_apb2opb_realize() - removed FSIMasterState object and fsi_opb_realize() - simplified OPBus - introduced fsi_aspeed_apb2opb_rw to fix endianness issue ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-15 20:31:55 +0000